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17c3056681bc6aec4c706cfeafef64ee960d5906
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315 Commits

Author SHA1 Message Date
OBattler
17c3056681 Finished fixing the VIA chipset required for the FIC VIP-IO2, added a version of the W83787F Super I/O chip with secondary IDE, fixed the W83787F IDE handler, made AT NVR initialize with 0xff rather than 0x00 by default (which is actually correct), and removed the FIC VIP-IO2 from the Dev branch. 2021-04-20 03:24:30 +02:00
RichardG867
dcbf4b5729 Merge branch 'master' of https://github.com/86Box/86Box 2021-04-17 16:43:32 -03:00
RichardG867
4c46d21924 Clean up 450KX formatting 2021-04-17 16:22:00 -03:00
OBattler
877cf20e01 Fixed DRB's on the Intel 420TX and 420ZX. 2021-04-17 04:54:33 +02:00
nerd73
8e3b09f323 Various 486 improvements 
- Added SL-Enhanced versions of Intel 486 CPUs and Enhanced AMD Am486DX2/DX4 CPUs
- Cleaned up the 486 CPU types and updated intel_4x0.c to reflect this
- Fixed some incorrect EDX reset and CPUID values
- Blacklisted non-SMM capable 486 CPUs on the Soyo 4SA2 motherboard
- Merged the non-OverDrive and OverDrive Intel DX4s because of further research confirming them to be functionally identical
- Removed SMM support on early 486 CPUs
 2021-04-15 21:38:03 -06:00
RichardG867
57c4bc485e Merge branch 'master' of https://github.com/86Box/86Box 2021-04-14 16:14:07 -03:00
RichardG867
80b1340454 Merge branch 'master' of https://github.com/86Box/86Box 2021-04-13 14:10:48 -03:00
RichardG867
71cbebb662 Work around P3V133 ACPI I/O space mapping issue 2021-04-13 14:05:18 -03:00
Panagiotis
0b7bec3831 Fixes on the Aladdin IV 2021-04-13 15:21:10 +03:00
OBattler
76f3f08d78 The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh. 2021-04-13 03:47:46 +02:00
OBattler
5a228ba8db Removed excess logging from intel_sio.c. 2021-04-13 02:35:13 +02:00
OBattler
3e5c2b88d5 The Intel 420TX and 420ZX chipsets now correctly have 57h as the SMRAM control register (identified by register write logging on the ASUS P/I-486SP3G) rather than 72h, fixes hangs and errors on the ASUS P/I-486SP3G. 2021-04-13 02:33:40 +02:00
Panagiotis
da82b11b29 Few minor changes on the Intel i450KX 2021-04-11 15:33:11 +03:00
OBattler
8b6f9707d5 More CPU fixes, and SMM now implemented on Cyrix Cx486 and Cx5x86 CPU's as well as on Intel/AMI SX, DX, and SX2 CPU's. 2021-04-11 07:25:08 +02:00
OBattler
28c95d88c2 The ALi M1487/89 now correctly clears SMI status on clearing bit 4 of register 0x30, fixes booting with 486DX2/iDX4. 2021-04-07 23:47:00 +02:00
Miran Grča
091b45c104 Merge branch 'master' into master 2021-04-06 07:24:30 +02:00
OBattler
0415351497 Added the Super PC/Turbo TX, ASUS P/I-486SP3, ASUS PVI-486SP3C, PC Partner MB520N, MSI MS-6168, and Packard bell Bora Pro. 2021-04-06 07:17:38 +02:00
Panagiotis
8edf104668 Fixed build error 2021-04-05 22:37:27 +03:00
Panagiotis
5d68fa68c0 Implemented the OPTi 822 VLB to PCI bridge 
Needed for early OPTi Pentium's but also 486's like the Packard Bell PB450 PCI. IRQ routing is hacking though!!
 2021-04-05 22:28:04 +03:00
Panagiotis
f29cd37b35 Minor fix for the UMC HB4 2021-04-02 10:18:51 +03:00
Panagiotis
405b613667 Disable logging 2021-04-02 10:16:11 +03:00
Panagiotis
698d4ce8a7 Minor improvements on the ALi M1217 2021-04-02 10:15:27 +03:00
Panagiotis
5e24a55067 Minor changes for the Internal IDE of the SiS 5571 2021-03-31 14:30:10 +03:00
Panagiotis
e9c589e7bc SiS 5571 can now configure the ISA bus clock 2021-03-31 13:52:25 +03:00
Panagiotis
88165ae918 Fixes and Improvements on the SiS 5571 
- SMI is now properly provoked
- Removed default methods for registers
 2021-03-31 13:26:16 +03:00
OBattler
345a61fa7c Removed the redundant mem_write_null* functions (the few mappings that use them, now use NULL pointers instead) and made the _phys function used by DMA not write to the exec buffer if the address has no write mapping (as in that case, it's clearly not intended to be writable), fixes #1332. 2021-03-30 02:16:01 +02:00
Panagiotis
d73011cd4c Early implementation of the Intel 450KX 
450GX & 450KX are the first chipsets intended for the i686 era of processors. Mostly they were used on workstations and servers but also a few general boards. This is an early implementation, not complete due to 86Box limitations in terms of memory handling.
 2021-03-28 21:06:06 +03:00
Panagiotis
f8910f4b19 Add the PCI & ISA Clock registers of the UMC 8886F 
Comply the UMC with the recent clock divider implementation.
 2021-03-26 11:34:59 +02:00
Panagiotis
050c16424c Seperated the UMC 8886, Added the UMC 8890 2021-03-25 11:01:54 +02:00
OBattler
3074d5b845 Cleaned up excess header includes from the chipset files and the ALI M1487/1489 is now correctly implemented (still Dev branched as I have not committed the machine files yet). 2021-03-24 20:03:20 +01:00
David Hrdlička
10cc122925 fix Clang/WinSDK warnings 2021-03-21 03:28:37 +01:00
Panagiotis
5fc10ecb50 Added missing brackets on the UMC HB4 
Fixes the IDE controller on the HOT-433A.
 2021-03-16 12:51:12 +02:00
Panagiotis
68e22e0c6d Hardcode cache size of the UMC HB4 to 512KB 
Fixes Cache freeze issue on the HOT-433A.
 2021-03-16 10:24:36 +02:00
Miran Grča
82b26f75be Merge pull request #1303 from richardg867/master 
AGP and clock control
 2021-03-15 22:50:31 +01:00
RichardG867
ca354f5854 Fix M1543 PCI slot mess 2021-03-14 20:29:46 -03:00
RichardG867
7cdceb056f Add ISA speed control to PIIX and VIA southbridges, and M6117 SoC 2021-03-14 19:44:09 -03:00
RichardG867
0f80e956d5 Add PCI and AGP speed control to i4x0 and VIA northbridges 2021-03-14 19:43:25 -03:00
Panagiotis
7c6e5bda4a First batch implementation of the UMC HB4 chipset 2021-03-13 11:44:07 +02:00
Miran Grča
8d5f32a3e5 Merge pull request #1279 from tiseno100/master 
Sanitize some old chipset code (Part 3)
 2021-02-15 03:03:58 +01:00
Panagiotis
988478a095 Tiny typo fix 2021-02-14 11:57:03 +02:00
Panagiotis
db4ef02a88 Unite the E & F segment recalcs into one Macro 2021-02-14 11:55:16 +02:00
Panagiotis
41cd6b48f8 More work at the Shadow recalc code of the Python 
Divided and documented into multiple macros
 2021-02-14 11:46:22 +02:00
Panagiotis
54a36d82b9 Shadow recalc on the Python doesn't need ternaries 2021-02-14 11:14:11 +02:00
Panagiotis
8b7d643452 Sanitize some old chipset code (Part 3) 
Fixed the Indentation of the Intel 82335, removed useless includes and numerous bugfixes on the OPTi Python.
 2021-02-13 12:31:04 +02:00
EngiNerd89
56f794e66c Merge branch 'master' of https://github.com/86Box/86Box.git into EngiNerd 2021-02-11 20:10:43 +01:00
EngiNerd89
a2c53e1a94 Re-added fully complete and working Olivetti and NCR 386SX-class machines. 
Moved Olivetti M290 to dev branch.
(Very) partially implemented Olivetti EVA gate array (used in M290).
 2021-02-11 19:07:24 +01:00
RichardG867
1f3f204301 Add stpc.c to compilation list 2021-02-08 17:21:52 -03:00
RichardG867
23fe2b454a Disable M6117 logging 2021-02-08 17:17:30 -03:00
RichardG867
5481d48bd7 Merge branch 'master' of https://github.com/86Box/86Box 2021-02-08 17:02:30 -03:00
EngiNerd89
f026ac6eea Merge branch 'master' of https://github.com/86Box/86Box.git into EngiNerd 2021-02-07 00:24:21 +01:00