Added the Mach8 and Mach32 ISA/VLB/PCI cards (initial implementation and MCA coming soon for the Mach32) and their corresponding EEPROM's.
Added INMOS XGA ISA card and updated the SVGA core to reflect its mapping as well as the Mach8/32 mapping when in 8514 monitor mode.
Mark the XGA button as already checked and locked when a standalone XGA BIOS card is present like the INMOS one. (QT only)
Same concept as above, but applies to the Mach8 and 32 for the 8514 option as well. (QT only)
Corrected 8bpp mode under Win2000 as well so that it no longer glitches.
VT2 is PCI only, so use its PCI timings only.
Small cosmetic fixes in the if's of the linear apertures of said card.
24bpp mode will be unthreaded while the rest of the bpp's is left intact, this is due to desyncing in 24bpp mode in NT 3.1's 24bpp drivers.
Mix patterns are drawn at the correct position now instead of backwards.
Better handling of subsys/subcntl side.
As usual, better handling of the VGA on/off passthrough.
Better handling of the accelerator pitch (TODO: need a way to properly identify 640x480x256 in the pitch side).
XGA: Fix crash when (S)VGA cards not selected as the primary display (e.g.: EGA, CGA. etc).
Better handling of the VGA on/off passthrough (vga_on variable).
MCA side: to avoid lfb issues, bit 0 of POS4 will be always enabled regardless of the ram size (most software uses the >16MB memory method).
Better handling of the BIOS ROM mapping and Memory Mapped I/O during the MCA PS/2 POST and resets, fixes 40 25 hang (once and for all).
Re-organized the ROM loading in ISA mode.
Also fixed are the blitter patterns in 8/15/16bpp modes by re-ordering (if it's the right term) the pixels of the Y pattern coordinates (code lines are from 1165 to 1183).
And properly implemented X/Y Count control routing blitters, fixes anything that uses software Bresenham and/or polygon stuff.
Required for 64KB-variant 640x350 2bpp modes (BIOS modes 0x0F, 0x10).
This does need some address decoding fixes to break the 16K-word barrier, though - those are coming.
