S3 (all): Fixes to the commonly used accel commands (0, 1, 2, 6, 7) to make the OS/2 software cursor to not bug on the left edge of the screen.
TGUI: Reworked the non-bitblt commands as well as the accel pitch and bpp modes.
Added the AT&T 2xc498 Precision RAMDAC.
Added 1MB configurations to the Cirrus Logic GD5434 as well as re-organized the memory size options of the other Cirrus cards.
Separated the et4000w32/i blitter from the standard et4000w32p blitter and properly implemented the X/Y Count route.
Added several Diamond Cirrus cards.
Added Number Nine S3 cards (868 and 968-based).
Fixed the WD90c30 1MB modes.
Re-organized the video card names.
Improved the banking of the ATI 28800-5 cards (VGA Charger and VGA Wonder XL).
Improved the skew and horizontal display of some of the ET4000W32P cards as well as the cursor.
Made the Oak OTI 077 and PVGA WD90c30 cards use the Sierra 11487 (actually a clone is used in the real cards).
For the WD90c30, changed the way the hack is involved.
Reverted some changes of the S3 Vision/Trio that originally made glitches, now the glitches are gone and the accelerator renders fine.
Re-organized the Sierra 1148x RAMDAC's and added the 11486 (Mark 1).
MCA SVGA cards use the full 32-bit mapping.
Properly fixed text/graphics mode of the S3 pre-ViRGE cards.
PIX TRANS cleanups.
Added a sanity check to banking, per bit 0 of CRTC31.
Initial implementation of Enhanced 4-bit mode.
911/924 chips use CRTC43 bit 3 for enabling 15/16bpp mode.
fb_only variable used correctly as of now (depending if on 4bit or 8bit+ modes).
S3 ViRGE changes part 2:
Made the Trio3D/2X AGP use the PCI_ADD_AGP part accordingly
RAMDAC changes:
Sierra 11483 and 11487 don't have an RS2 signal so the four times reading scheme of 0x3c6 is used instead, per documentation.
Fixed AT&T 49x bpp selection.
Other changes:
Fixed remaining rendering issues with the Radius SVGA HT209 card.
Added dword addressing to pix trans reads.
Added VRAM masking to the hardware cursor.
Properly fixed the FIFO slots.
Width set to 1024 by default in the 911 and 924 chips.
Reintroduced dword mode for chips before Trio64V+.
The Trio64V+ and Trio64V2 chips now have svga->fb_only (which is strongly required by the mapping and the modes) and packed_chain4 set, just like the ViRGE.
