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185 Commits

Author SHA1 Message Date
OBattler
795a6017d2 PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy). 2020-10-14 23:15:01 +02:00
nerd73
6f5cc1f028 Undo anabate's VIA C3 changes entirely 
There are no emulated chipsets which officially support 133 MHz FSB.
 2020-09-22 23:57:52 -06:00
OBattler
7bff0cdc89 Fixed a typo in the CPU tables. 2020-09-23 07:23:38 +02:00
anabate123
f97a7aadeb Update cpu_table.c 2020-09-22 19:38:24 -04:00
anabate123
fadbd807ef Update cpu_table.c 2020-09-22 19:32:07 -04:00
RichardG867
4107c2090e Fix M6117 clocking mistake; the CPU has a clock divider(!) 2020-09-08 22:19:36 -03:00
RichardG867
a129291a0d Change STPC CPU table to better values, more in line with the 486 CPU list and BIOS identification naming schemes 2020-09-08 22:10:13 -03:00
RichardG867
55b29db14b Finish M6117 implementation 2020-09-08 22:08:34 -03:00
RichardG867
0b8bd4e610 More documentation on VPCEXT opcodes, as requested 2020-07-27 12:24:31 -03:00
RichardG867
a8855733ec Implement more VPCEXT opcodes 2020-07-26 17:49:12 -03:00
OBattler
70dd4ba3be Generic MO Device ID changes and implemented the VPCEXT instructions (on the Virtual PC 2007 VM only). 2020-07-25 05:14:06 +02:00
nerd73
e7b8bda771 Implement clock-dividing for FPUs on clock-multiplied 386s 
This is done by making it so that if the FPU is not at least a 487SX, the clock cycles are multiplied by the CPU multiplier.
 2020-07-22 22:17:58 -06:00
OBattler
6a4a57bba8 Added an extern declaration of stdlog to x86seg.c. 2020-07-22 18:23:21 +02:00
OBattler
eba7d798a0 Merged the two copies of x86seg.c, finishing the mergers started in February. 2020-07-22 17:46:43 +02:00
OBattler
1ff36987a2 Merged the two copies of x86_ops_shift.h. 2020-07-22 16:45:46 +02:00
OBattler
b52e91f031 Fixed the FPU stuff and added the ability to select the 487SX. 2020-07-22 16:39:57 +02:00
OBattler
aeaf5ad34a Properly enabled SMM (and with the correct SMBASE) on AMD 486 CPU's. 2020-07-20 01:44:19 +02:00
OBattler
c7f4aabbf0 Fixed the previous fix. 2020-07-16 01:14:24 +02:00
OBattler
0b4b2b4d2f A number of recompiler fixes and put some of the timer/cycle-related changes behind #ifdef's as they are no longer used but someone may want to still try them out. 2020-07-15 18:30:27 +02:00
OBattler
10e16249fd Merged the two copies of x86_ops_call.h. 2020-07-15 03:37:44 +02:00
OBattler
39726915d3 Merged the two versions of x86_flags.h into one. 2020-07-15 03:22:28 +02:00
OBattler
a862bda04c Rewrote the recompiler interrupt checking in assembly (and removed it for the new dynamic compiler because the requires uops are not present), brings performance back up, and also did a number of CPU-related clean-ups (mostly removal of dead variables and associated code). 2020-07-13 19:46:19 +02:00
OBattler
0cd0d83cee Both recompilers now check for interrupt after every instruction and exit the block if one has happened. 2020-07-13 01:23:40 +02:00
OBattler
099fd2fc34 Properly fixed update_tsc(). 2020-07-12 23:51:56 +02:00
OBattler
38828bdc3b TSC update cycle fixes. 2020-07-12 21:05:46 +02:00
OBattler
974a7ae4f1 Fixed cycles accumulation in update_tsc() when cache is enabled (and the actual recompiler kicks in), and also fixed a warning in the 82091AA code. 2020-07-12 20:01:16 +02:00
RichardG867
5a34bab430 Fix build 2020-07-07 16:08:36 -03:00
RichardG867
2efdc9aafc Change non-doubled STPCs to non-doubled Cx486DX 2020-07-07 16:06:40 -03:00
RichardG867
fef6e7f082 Set proper CPU speeds for each STPC machine 2020-07-07 16:05:05 -03:00
RichardG867
5e18163b2e Fix STPC CPU identification 
Let port 22h/23h registers >= 0xc0 fall through to the Cyrix port 22h/23h code in cpu.c
 2020-07-07 15:38:34 -03:00
RichardG867
18a3e4795c Add STPC 75 to CPU table 2020-07-06 21:11:53 -03:00
RichardG867
8536f93dfc Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/cpu/cpu.c
 2020-07-06 19:00:31 -03:00
RichardG867
c1dd844747 Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/machine/machine_table.c
#	src/win/Makefile.mingw
 2020-07-06 18:47:50 -03:00
RichardG867
11114c97d2 Initial implementation of STPC chipsets and machines 2020-07-06 18:45:34 -03:00
nerd73
18368203ec Fix issues with Cyrix DX2/DX4 CPUs 
Fix some issues with the Cyrix DX2 & DX4 CPUs and restore the Cyrix 6x86 for dev-branch builds.
 2020-07-06 13:01:52 -06:00
David Hrdlička
254c8024f8 Fix MSVC build 2020-07-06 20:20:07 +02:00
nerd73
064acae3fc Fix MSRs on the IBM 386/486 CPUs 
Also give the IBM 386SLC 'isibm486' as it is believed to identify as a 486 to software.
 2020-07-02 20:34:18 -06:00
RichardG867
f565362a41 Undo local changes to cpu.c 2020-07-02 21:44:28 -03:00
RichardG867
5d5883ac0d Merge branch 'master' of https://github.com/86Box/86Box 2020-07-02 21:42:52 -03:00
RichardG867
b043f1867b Genesys Logic GL518SM hardware monitor 2020-07-02 21:42:31 -03:00
nerd73
a9e0dd247a Implement IBM 486 MSRs 
Implement the MSRs supported by the IBM 386SLC/486SLC/486BL.
 2020-07-02 10:09:55 -06:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
TC1995
33eec2ef52 Removed last instances of the deskpro 386 code. 2020-06-17 14:49:23 +02:00
TC1995
f62fc73862 (Re-)added the Deskpro 386, but only in the development/incomplete section of the code definitions. 
Selected XT and AT clones can use either their built-in FDC controller or an external one (the IBM AT and Compaq AT machines don't support booting from a 1.44M floppy so this makes the external floppy useful).
Added the FDC to the Adaptec AHA-154xCF ("2" variant) and defaulted to None to keep compatibility with existing FDC's.
 2020-06-17 00:32:48 +02:00
OBattler
3e8d27d015 Fixed FPU on RapidCard onwards (fixes OS/2 on RapidCard onwards to no longer think it's a 287) and renamed the Built-in FPU to Internal to be consistent with the rest of the emulator. 2020-06-15 22:49:30 +02:00
OBattler
af06ba62c0 Hooked up the new FPU type selection to the UI. 2020-06-15 21:21:26 +02:00
OBattler
6d888cf869 Merge pull request #809 from nerd73/master 
Preliminary port of PCem's FPU timing emulation
 2020-06-15 17:12:08 +02:00
OBattler
6c6cae0965 Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged). 2020-06-15 17:08:42 +02:00
nerd73
a4d33513e4 Preliminary port of PCem's FPU timing emulation 2020-06-15 04:11:12 -06:00
tiseno100
a7cdbc50c0 Disable CPU logging 2020-06-15 11:38:00 +03:00