5 Commits

Author	SHA1	Message	Date
OBattler	6e2b91c3d1	Pretty much all timer counters are now 32-bit again; ... Fixed FDI stream parameters passed to the 86F handler, FDI stream images now read correctly again; The National Semiconductors PC87306 SuperI/O chip now supports enhanced FDC mode.	2016-11-07 06:39:20 +01:00
OBattler	d860ea79ed	Timer enable switches are 64-bit; ... Floppy reads/writes now correctly finish at gaps; Sector-based reads/writes no longer cause a delay when signaling finish.	2016-08-21 03:42:24 +02:00
Jackson Bryn	291ac890e2	Add copyrights for all files to comply with the GPL v2.	2016-08-14 22:27:13 -04:00
OBattler	b78b2fecaa	Timer counters now 64-bit; ... Cleaned up floppy code a lot and reverted to single poller; Fixed segment present bit and limit checking at read/write within segment; The ASUS boards now have memregs too; RTC code improved based on suggestion by Sarah Walker; Fixed SVGA odd/even emulation and added chain odd/even support; Removed non-existent CPU's.	2016-07-19 02:44:32 +02:00
OBattler	fd2a5bc9f5	Initial submission of the PCem-Experimental source code.	2016-06-26 00:34:39 +02:00