Commit Graph

78 Commits

Author SHA1 Message Date
Cacodemon345
54bc9dc58c 808x: Make sure all 8018x opcodes are marked as handled (#19) 2022-09-10 05:39:39 -04:00
Cacodemon345
fc2fac4c73 More i8080 + NEC changes (#18)
* More i8080 changes

* Fix compilation

* More foundational i8080 work

* Switch to __builtin_parity for parity flag setting

Fix some incorrectly implemented instructions
2022-09-10 04:50:50 -04:00
Cacodemon345
c2cc656103 Fix NEC BCD instructions (#15) 2022-09-08 14:26:05 -04:00
Cacodemon345
25b2e16a27 NEC INM/OUTM instructions (#14) 2022-09-07 15:58:42 -04:00
Cacodemon345
7b29c30819 Implement immediate IMUL operands (#13)
* Implement immediate IMUL operands

Implement PUSH segment underflow behaviour on SP = 1 values for 8018x

* Limit bit-shifts and rotates to 31 on Intel 8018x

* NEC/8018x ENTER/LEAVE instructions

* NEC/8018x bound checking instruction
2022-09-07 08:50:30 -04:00
Cacodemon345
2b0dff2ec6 Implement immediate versions of PUSH operations (#12)
Implement immediate versions of bit-shifting operations

Make word read/write operations not overflow when offset is 0xFFFF on 8018x
2022-09-06 16:59:39 -04:00
Cacodemon345
3dbfcf1fd3 NEC SUB4S and CMP4S instructions (#11)
* NEC SUB4S and CMP4S instructions

* Return to original IP properly in case of POP PS

* NEC REPC/REPNC instructions

* Make NEC BRKEM instruction a fatal for now

* Fix wrong segment addresses in some NEC instructions
2022-09-06 12:29:54 -04:00
Cacodemon345
e93cd46c78 NEC ADD4S instruction (#10) 2022-09-05 16:27:09 -04:00
Cacodemon345
323f7e7a62 NEC INS/EXT instructions (#9) 2022-09-05 06:18:10 -04:00
Cacodemon345
199bbed5ee NEC CLR1 instructions (#8)
Wraps up the fixed bitfield manipulation instructions
2022-09-04 16:00:29 -04:00
Cacodemon345
2280685526 NEC SET1 instructions (#7)
Mask the bit argument properly
2022-09-04 15:50:38 -04:00
Cacodemon345
db6eac6e2f Mark recently-added instructions as handled (#6) 2022-09-04 15:38:42 -04:00
Cacodemon345
6b55fa3d2e NEC NOT1 instruction (#5)
Fix bit value usage of TEST1 instruction
2022-09-04 15:25:08 -04:00
Cacodemon345
474ab60c97 NEC TEST1 instruction (#4) 2022-09-04 15:11:04 -04:00
Cacodemon345
71dde8658b Implement more NEC V20/V30 and 8018x instructions (#3)
* Implement more NEC V20/V30 and 8018x instructions

* PUSHA/PUSH R
* POPA/POP R
* RO(L/R)4 r/m (NEC only)

* Fix critical mistake
2022-09-04 12:30:21 -04:00
Cacodemon345
18d15758f5 Don't set ZF on MUL/MULU operations on NEC V20/V30 (#2) 2022-09-03 14:27:05 -04:00
Jasmine Iwanek
8ef1d28b2c Merge branch '86Box:master' into nec-v20 2022-03-18 15:05:25 -04:00
RichardG867
f57cbe36b1 GDB Stub: More progress 2022-03-16 00:33:01 -03:00
RichardG867
94be8cdfc6 GDB Stub: Initial commit 2022-03-12 20:20:25 -03:00
Jasmine Iwanek
6bccf983e5 Merge branch '86Box:master' into nec-v20 2022-02-20 21:08:06 -05:00
Jasmine Iwanek
4674756664 More newline and whitespace cleanups 2022-02-20 16:26:40 -05:00
Jasmine Iwanek
b4e5fec867 Merge branch '86Box:master' into nec-v20 2022-02-02 22:14:22 -05:00
OBattler
b3a8d0aaed And more. 2022-02-02 02:51:18 +01:00
OBattler
25e8801ede And more. 2022-02-02 02:46:11 +01:00
Jasmine Iwanek
a349823c7d Initial proddings at NEC V20/V30 2022-01-31 13:39:06 -05:00
linear cannon
04c89959f8 adjust CLOCK_CYCLES and related macros to handle fpu/iu concurrency
add CLOCK_CYCLES_FPU, which does exactly what CLOCK_CYCLES already did.

add CONCURRENCY_CYCLES, which sets fpu_cycles, which is the number of
available concurrent execution cycles that the integer unit can do
"free" work in while the fpu is executing.

adjust CLOCK_CYCLES so that if there are fpu_cycles, the cycle count is
subtracted from fpu_cycles instead of cycles, emulating the behavior of
these concurrent cycles being "free" as on real hardware.
2022-01-29 07:38:41 -08:00
OBattler
9ec4fd3bdd Fixed a CPU reset mess. 2021-12-19 19:14:21 +01:00
OBattler
0c4003caa3 Added the C&T 82C100 chipset needed by the Victor V86P. 2021-09-07 23:41:17 +02:00
OBattler
586066d891 Made NMI's always auto-clear, will revert if it makes things worse. 2021-09-02 15:24:17 +02:00
OBattler
c370ae7e18 CPU and MMU cleanups and fixes, and non-Debug builds are now stripped again. 2021-04-10 07:18:47 +02:00
OBattler
d31bca5279 Removed two void returns (how that even valid?!) from the 808x code. 2020-12-12 10:18:00 +01:00
OBattler
1bc5eca8fd 808x PIC acknowledges now incur bus access wait states. 2020-12-02 05:52:28 +01:00
OBattler
f9c2f04a52 808x fixes - 8088mph works normally again. 2020-11-28 07:02:38 +01:00
OBattler
6e233f4ac8 SDL renderer improvements and fixes and added SDL OpenGL option;
Various performance improvements;
Fixed USB UHCI HCHalt;
Cirrus Logic CL-GD 5422/24 fixes and removed them from the Dev branch;
The Storage controllers sections of Settings now has its own corresponding section of the configuration file;
Fixed the AT clock divisors for some Pentium OverDrive CPU's;
Added the ACPI RTC status (no ACPI RTC alarm event yet).
2020-11-26 18:20:24 +01:00
OBattler
ab8f9d3866 The new 808x-only memory read/write functions now apply the RAM mask to the address so addresses now correctly wrap around 1 MB, fixes #1062;
More 808x bug fixes.
2020-11-17 02:20:19 +01:00
OBattler
bf4b5b781f Implemented PIC IRQ latch and delay (per the datasheet), IBM PCjr now works without a workaround delay in cpu/808x.c which was therefore removed; also redid memory and I/O accesses in cpu/808x.c to fix word writes on 8086. 2020-11-17 00:25:28 +01:00
OBattler
0faf6692c9 WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED.
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite;
Added device.c/h API to obtain name from the device_t struct;
Significant changes to win/win_settings.c to clean up the code a bit and fix bugs;
Ported all the CPU and AudioPCI commits from PCem;
Added an API call to allow ACPI soft power off to gracefully stop the emulator;
Removed the Siemens PCD-2L from the Dev branch because it now works;
Removed the Socket 5 HP Vectra from the Dev branch because it now works;
Fixed the Compaq Presario and the Micronics Spitfire;
Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470;
SMM fixes;
Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions;
Changed IDE reset period to match the specification, fixes #929;
The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset;
Added the Intel AN430TX but Dev branched because it does not work;
The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full);
Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types;
USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it);
Fixed NVR on the the SMC FDC37C932QF and APM variants;
A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX;
Some ACPI changes.
2020-11-16 00:01:21 +01:00
OBattler
cfb559de13 Made the 808x interrupts delay again, fixes PCjr (TODO: Find why exactly that's needed because it sounds like a hack to me);
Fixed compiling of the PIC code with logs enabled;
A number of bugfixes in cpu/x86seg.c, fixes OS/2 1.0.
2020-11-01 04:21:55 +01:00
OBattler
080b8c12be Fixed the DAA instruction on 808x, fixes the Generic XT Clone BIOS POST. 2020-10-30 18:19:48 +01:00
OBattler
795a6017d2 PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy). 2020-10-14 23:15:01 +02:00
OBattler
aeaf5ad34a Properly enabled SMM (and with the correct SMBASE) on AMD 486 CPU's. 2020-07-20 01:44:19 +02:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
OBattler
ca55e2a12a More reorganization and finally merged the two makefiles. 2020-06-13 12:32:09 +02:00
OBattler
60ba71cb4b Renamed the three CPU folders to their final names. 2020-06-13 10:54:05 +02:00
OBattler
490c04fcae Current WIP code. 2020-02-29 19:12:23 +01:00
OBattler
ebf0d1ef3a Fixed MSR's on AMD CPU's - the VIA machine now works without issues with the high-speed AMD CPU's. 2020-01-16 20:49:58 +01:00
OBattler
e44e60c660 Fixed the fourth batch of problems. 2020-01-15 05:24:33 +01:00
nerd73
fb050149e3 Update 808x.c 2019-12-17 06:45:53 -07:00
nerd73
4e8bcfd6ad Add files via upload 2019-12-16 18:10:19 -07:00
OBattler
c6ee6f48de Removed an unused table from the XT MFM controller code;
808x prefetch queue is now always cleared on soft reset (as it should be due the changing CS:IP).
2019-10-21 03:24:36 +02:00