OBattler
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c30d5d90b7
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PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
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2023-08-07 03:04:52 +02:00 |
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Jasmine Iwanek
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998cfe5cc8
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Constification
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2023-07-25 17:59:24 -04:00 |
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Jasmine Iwanek
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922c4335ae
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Next round of sonarlint cleanups
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2023-06-27 21:17:13 -04:00 |
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Jasmine Iwanek
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21adfd4d50
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Next round of sonarlint cleanups
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2023-06-26 18:28:13 -04:00 |
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Jasmine Iwanek
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6c1e4a8e2c
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Some code smell fixes from sonarlint
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2023-05-15 19:25:56 -04:00 |
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Jasmine Iwanek
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bd75bc141a
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Header cleanups
Tabs to spaces
Consistency
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2022-11-13 21:15:47 -05:00 |
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Jasmine Iwanek
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fab1632cee
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Fixes almost all the logging options which were previously broken
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2022-10-27 11:23:10 -04:00 |
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Jasmine Iwanek
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3753a9f8b2
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clang-format in src/chipset/
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2022-09-18 17:19:21 -04:00 |
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OBattler
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f6fef765d7
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Chipsets.
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2022-07-16 02:58:37 +02:00 |
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Jasmine Iwanek
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a52f0cca79
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src/chipset
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2022-03-13 09:21:08 -04:00 |
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Jess Lovelace
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f18615ae87
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refactored device_t and all declarations
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2022-02-02 16:31:22 -05:00 |
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OBattler
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1c2d1e702b
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Assorted changes and bugfixes and added the two IMS 8848 machines.
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2021-10-09 17:37:09 +02:00 |
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Alexander Babikov
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0208c7560f
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Fix incorrectly set 7.16 MHz clock speeds on some chipsets
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2021-04-26 04:21:29 +05:00 |
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Panagiotis
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ba92f1df34
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Finalize the SiS Pentiums
- Implemented the SiS 5511
- The SiS 5571 can safely go off Dev Branch now
- Few fixes on the SiS 5598
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2021-04-25 13:23:41 +03:00 |
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