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7a5ea200bb6545f72ff12e5912e561c9e4dd45d6
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41 Commits

Author SHA1 Message Date
OBattler
7a5ea200bb Made the QDI FMB's PIIX no longer use MIRQ for the secondary IDE controller, makes the secondary IDE controller work. 2022-10-25 02:38:06 +02:00
Jasmine Iwanek
3753a9f8b2 clang-format in src/chipset/ 2022-09-18 17:19:21 -04:00
OBattler
dcd7cc9047 And more. 2022-07-16 04:09:49 +02:00
OBattler
c58360df3e Chipsets. 2022-07-16 03:21:09 +02:00
OBattler
f6fef765d7 Chipsets. 2022-07-16 02:58:37 +02:00
Jasmine Iwanek
a52f0cca79 src/chipset 2022-03-13 09:21:08 -04:00
Jasmine Iwanek
4674756664 More newline and whitespace cleanups 2022-02-20 16:26:40 -05:00
Alexander Babikov
e8456cc5ca Change the internal name for the PIIX3 variation for boards with I/O APIC 2022-02-13 20:23:10 +05:00
OBattler
e9fbbf41d0 Added the version of PIIX3 for boards with I/O APIC that wires secondary IDE IRQ directly to legacy IRQ 15 instead of MIRQ0. 2022-02-05 13:43:24 +01:00
Jess Lovelace
f18615ae87 refactored device_t and all declarations 2022-02-02 16:31:22 -05:00
OBattler
10a257749f Fixed Intel PIIX and VIA PIPC trap SMI# function calls. 2021-10-19 18:19:29 +02:00
OBattler
a394a33500 Conflict resolution. 2021-10-19 18:18:15 +02:00
RichardG867
04bea78e5e PIIX: Implement drive separation on IDE I/O traps 2021-10-19 00:17:27 -03:00
RichardG867
8e823f125c PIIX: Remove I/O traps on close 2021-10-18 23:56:40 -03:00
RichardG867
8dd26d5776 Fix some logging stuff 2021-10-18 23:29:30 -03:00
RichardG867
e05aab152a Implement I/O port traps on PIIX and VIA ACPI 2021-10-18 21:59:12 -03:00
RichardG867
878c92bf7f ACPI: Rework suspend types and remove bogus PMCNTRL mirrors (those are SMI traps instead) 2021-10-18 15:05:38 -03:00
RichardG867
6bf299cd41 Implement undocumented PMCNTRL mirrors on VIA 596 (unconfirmed), 686 (confirmed) and PIIX4 (unconfirmed) ACPI 2021-10-16 21:36:58 -03:00
OBattler
626e8e58bb Implemented a PIIX register written to by the ZAPPA that is officially reserved on PIIX (but otherwise exists on PIIX3). 2021-09-17 02:54:19 +02:00
OBattler
67367798a7 Merged various SMC FDC67C6xx Super I/O chips into one file, re-added the UMC88xx 486 chipsets (and four machines for it) based on work by tiseno100 and my own work, various other fixes, and added quite a few machines (including the AOpen AP5VM which now works), also added the remaining ALi M6117 machine (Protech SBC with Award BIOS), and made the Intel Advanced/ATX's on-board S3 Trio64V+ work, as well as the on-board S3 Trio64/V2 of the two Compaq Presarios. 2021-08-21 18:19:10 +02:00
Miran Grča
8ca1328c7e Merge pull request #1571 from 86Box/master 
Bring the branch up to par with master.
 2021-08-02 06:58:22 +02:00
OBattler
f79b11cd9a PIIX3 fixes. 2021-07-27 03:42:56 +02:00
OBattler
e864aa2edc PIIX IDE non-bus master BAR's are now only writable on the SMSC Victory/66. 2021-07-26 05:02:40 +02:00
OBattler
a896953dd5 Current WIP ALi work. 2021-07-04 18:16:35 +02:00
OBattler
73bdd27ba8 Fixed PIIX MIRQ routing so MIRQ1 routing is no longer incorrectly applied to MIRQ0. 2021-06-10 05:07:32 +02:00
OBattler
50af9387f8 Makes PIIX board configuration registers work again - fixes deep beeps on Intel Advanced/ATX. 2021-06-06 23:56:21 +02:00
OBattler
50e32b6873 Temporarily disabled the second PIT on the PIIX and SIO to gain some performance back. 2021-04-29 23:46:44 +02:00
OBattler
49b1753dd0 Corrected PIIX4 ACPI GPIREG defaults to fix the ASUS P2B-LS. 2021-04-27 04:39:46 +02:00
OBattler
76f3f08d78 The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh. 2021-04-13 03:47:46 +02:00
OBattler
3074d5b845 Cleaned up excess header includes from the chipset files and the ALI M1487/1489 is now correctly implemented (still Dev branched as I have not committed the machine files yet). 2021-03-24 20:03:20 +01:00
RichardG867
7cdceb056f Add ISA speed control to PIIX and VIA southbridges, and M6117 SoC 2021-03-14 19:44:09 -03:00
OBattler
0faf6692c9 WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED. 
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite;
Added device.c/h API to obtain name from the device_t struct;
Significant changes to win/win_settings.c to clean up the code a bit and fix bugs;
Ported all the CPU and AudioPCI commits from PCem;
Added an API call to allow ACPI soft power off to gracefully stop the emulator;
Removed the Siemens PCD-2L from the Dev branch because it now works;
Removed the Socket 5 HP Vectra from the Dev branch because it now works;
Fixed the Compaq Presario and the Micronics Spitfire;
Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470;
SMM fixes;
Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions;
Changed IDE reset period to match the specification, fixes #929;
The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset;
Added the Intel AN430TX but Dev branched because it does not work;
The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full);
Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types;
USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it);
Fixed NVR on the the SMC FDC37C932QF and APM variants;
A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX;
Some ACPI changes.
 2020-11-16 00:01:21 +01:00
OBattler
f1b59303ab Implemented VIA PIPC device PCI reset function and improved that of PIIX. 2020-10-20 18:38:41 +02:00
OBattler
a81f9514b6 Assorted fixes related to the SMSC southbridge - now all four IDE devices get UDMA-66. 2020-10-13 22:44:22 +02:00
OBattler
f465066ed2 The SMSC southbridge now initializes IDE regiters 0x45 and 0x46 to the correct values. 2020-10-13 21:49:55 +02:00
OBattler
2569bcbf43 Added a sanity check on write to PIIX4(E) DDMA base PCI registers. 2020-09-08 03:42:42 +02:00
OBattler
949e145be3 Rewrite of AT keyboard controller polling. 2020-08-04 04:01:54 +02:00
OBattler
f696dc69ad Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine. 2020-07-08 04:24:25 +02:00
OBattler
7d4813aea7 PIIX now disables IDE on hard reset, fixes the AP440FX hard reset slowness. 2020-06-15 20:06:03 +02:00
OBattler
6c6cae0965 Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged). 2020-06-15 17:08:42 +02:00
OBattler
9c6f0d806e A slight reorganization of the source tree and fixed a warning in disk/mo.c. 2020-06-13 10:17:57 +02:00