Commit Graph

818 Commits

Author SHA1 Message Date
OBattler
95e98b1b20 Added the two Silicon Valley machiens and fixes 386 FPU flag on reset. 2025-08-14 16:29:09 +02:00
Jasmine Iwanek
a96146742e Fix another warn in 808x.c 2025-07-28 01:52:40 -04:00
Jasmine Iwanek
6d6d5931bf Fix several codeql warns 2025-07-27 20:59:55 -04:00
Cacodemon345
916533499a Add 10ms interval option (not exposed yet to UI)
Fix percentage counter
2025-07-09 12:59:16 +06:00
Cacodemon345
ddea070faa Fix cycle period of dynarec 2025-07-08 16:51:53 +06:00
OBattler
773ebf6254 Fix V20/V30 CPU speeds. 2025-07-08 05:59:04 +02:00
OBattler
42c0077703 808x: Suspend trap for 1 instruction after POPF and do not do it after IRET. 2025-07-08 05:21:44 +02:00
OBattler
a2354599c6 Vx0: Always resume from interrupt on HLT, even if I_FLAG is not set. 2025-07-08 05:08:23 +02:00
OBattler
4a468246cc 808x: Rename wait() to wait_cycs() to avoid conflict with the Apple SDK. 2025-06-30 00:52:00 +02:00
OBattler
ad5aa6e52f Attempt to undefine wait to avoid the conflicts on Mac. 2025-06-30 00:18:59 +02:00
OBattler
e601f25805 x87: Fix the rounding_modes warnings. 2025-06-30 00:17:33 +02:00
Cacodemon345
b44042ef1c x86-specific FADD (SSE2 version) 2025-06-30 02:08:48 +06:00
Cacodemon345
96734590ca x86-specific FADD implementation 2025-06-30 01:10:58 +06:00
Jasmine Iwanek
026f765495 Some codeql fixes 2025-06-29 00:12:06 -04:00
Jasmine Iwanek
3a26b9d46b Many warning fixes 2025-06-28 23:54:07 -04:00
OBattler
25f0a26ea1 Vastly improve the ALi M1409 emulation (all of shadow RAM now work, as does bus speed and external cache setting), and fix the "Writing unimplemented Cyrix register FF" error as well. 2025-05-29 09:45:49 +02:00
OBattler
b3147ee473 LOCK instruction: ensure it is always illegal on opcodes 90h and ECh. 2025-05-18 02:20:18 +02:00
OBattler
ddd271f6ee Honore the fixed bits of flags when pushing them to the stack, fixes #5093. 2025-05-17 21:02:06 +02:00
OBattler
a0b80e04cd Remove the unused mmu_perm stuff. 2025-05-06 03:18:46 +02:00
OBattler
1e81473d34 Fix MMX_ENTER() exceptions. 2025-05-05 05:59:20 +02:00
OBattler
9b93e71b23 #included the missing plat_fallthrough.h. 2025-04-27 18:57:21 +02:00
OBattler
5b4db319bf Opcode D6 is now an alias of opcode D7 (XLAT) on NEC Vx0, closes #5516. 2025-04-27 18:50:45 +02:00
Cacodemon345
e076c1051d Fix x87_op being outside of structure, fixing crashes in ARM64 NDR 2025-04-26 23:23:34 +06:00
OBattler
b15f25ffa4 Fixed old recompiler compiling in a kludgy way because it appears there's no STORE_IMM_ADDR_W. 2025-04-22 09:46:58 +02:00
OBattler
8790395a05 Fix the FXSAVE/FXRSTOR instructions. 2025-04-22 09:13:38 +02:00
Miran Grča
a434a98495 Merge pull request #5455 from Torinde/patch-3
VIA Cyrix III (Samuel) - add codename
2025-04-21 02:28:23 +02:00
OBattler
8aa15fa21f The update value handler should be at Pentium Pro, not Cyrix Cx6x86. 2025-04-11 20:27:41 +02:00
OBattler
95a6aa0bdf Fix the LxS fix again. 2025-04-11 19:29:40 +02:00
Torinde
9032af002d VIA Cyrix III (Samuel) - add codename
To distinguish from Cyrix-heritage Joshua CPUs. #5451
2025-04-09 12:17:50 +02:00
OBattler
3b5966eb46 LDS/LES/LFS/LGS/LSS: Fix segment wraparounds in 16-bit address mode. 2025-04-07 06:03:19 +02:00
RichardG867
4bd374a7df Don't apply the Deschutes cacheability fix to Covington 2025-04-02 16:55:57 -03:00
RichardG867
f56f636248 Report 4 GB cacheable memory on Deschutes CPUs, fixes modern Linux limiting itself to 512 MB on some machines 2025-04-02 16:27:10 -03:00
Cacodemon345
abbae5efd2 Cleanups 2025-03-26 23:18:36 +06:00
Cacodemon345
ad4e90e345 Finally fix RETEM 2025-03-26 23:01:09 +06:00
Cacodemon345
2b107725bd Custom NMI handling for i8080 emulation 2025-03-26 20:17:13 +06:00
Cacodemon345
99e8d13afa Implement NEC V20/V30's i8080 emulation mode 2025-03-26 20:04:43 +06:00
OBattler
609f34cc49 Only flush write MMU cache on WP flag toggle as read and execute MMU cache is not affected by the flag. 2025-03-23 15:36:05 +01:00
Cacodemon345
a9c97abfb6 Pre-calculate pow table for FXTRACT instruction 2025-03-20 21:52:48 +06:00
OBattler
2cd99f0c70 X86 segmentation: apparently, the CPU can execute a data segment in some cases, used by LINK and CodeView, fixes #5283. 2025-03-19 07:54:54 +01:00
OBattler
395f23cf57 More Cyrix fixes. 2025-03-19 03:12:36 +01:00
OBattler
70dcdee72b Some Cyrix MII table/ID fixes and added some Cyrix CPU blocking for the NuPRO 592 and the P5MMS98. 2025-03-18 19:21:00 +01:00
OBattler
79134f3b21 Assorted Cyrix (and Codegen opcode Mod R/M passing table) fixes - fixes Windows 98 SE on Cyrix 6x86's with power management enabled. 2025-03-17 03:40:52 +01:00
OBattler
dd4e493f64 Applied the fix to the optional 486 implementation as well. 2025-03-17 00:07:41 +01:00
OBattler
52a16529dc 386 Interpreter: Fix execute breakpoints. 2025-03-16 23:54:55 +01:00
OBattler
9f200fe2e8 386 Interpreter: Check for debug breakpoint before segment limit and presence checking. 2025-03-16 21:20:15 +01:00
Miran Grča
3058acff0c Merge pull request #5358 from Cacodemon345/x87-fpu-interpreter
Use `fpclassify` for FXAM instead of manual comparison
2025-03-16 18:40:23 +01:00
OBattler
1c5d432d3c Disable special segment selector pushing behavior on Pentium onwards, fixes MSVC builds of ReactOS. 2025-03-16 18:37:32 +01:00
Cacodemon345
271a125301 Use fpclassify for FXAM instead of manual comparison
NaN detection for interpreter floating point compare on ARM64
2025-03-16 23:33:40 +06:00
OBattler
aef06552fb Some missing breaks in the Cyrix register writes. 2025-03-14 15:34:37 +01:00
OBattler
78f50c5b04 Move the Cyrix 6x86 out of the Dev branch. 2025-03-06 00:17:16 +01:00