Commit Graph

21 Commits

Author SHA1 Message Date
tiseno100
82b73e7941 SuperMicro WinBios 440LX & 440BX + Slot 2 440GX bringup 2020-05-12 19:33:26 +03:00
tiseno100
811fac7064 Corrected the Mendocino multipliers
Now the Mendocino's use the correct intended multipliers.
2020-05-05 13:29:59 +03:00
nerd73
9bc74bbf00 Add the ECS P6KFX-A, a 440FX Slot 1 machine.
Adds the ECS P6KFX-A as well as appropriate CPU tables for an early Slot 1 motherboard without Deschutes or 100 MHz FSB support. Also fixes a minor bug with 266 MHz Pentium IIs and ISA clock frequencies.
2020-04-16 18:30:37 -06:00
OBattler
275dd5a2f7 ACPI, SMM, and PIIX fixes, fixes quite a few boards, also fixed the Via Apollo series northbridge ID's, some CPU instructions on both 808x and 286+, and added SMM to 486's (Intel and AMD), WinChip and WinChip 2, and VIA Cyrix III, also removed the TC430HX and the Toshiba machine from the Dev branch. 2020-04-16 21:56:19 +02:00
OBattler
d75e901a83 Moved the Intel i686 CPU's and related machines out of the Dev branch. 2020-04-10 20:01:26 +02:00
OBattler
2a0b3eb9c5 Added PAE, ported K6, P6, and WinChip 2 timings to the old recompiler, added a bunch of CPU's to the old recompiler, done some x87 fixes for both recompilers, added PAE, and fixed root directory entries for single-sided 5.25" DD floppies in the New Floppy Image dialog. 2020-04-10 01:08:52 +02:00
David Hrdlička
a505894a10 Move all include files to src/include
- 86Box's own headers go to /86box
- munt's public interface goes to /mt32emu
- all slirp headers go to /slirp (might want to consider using only its public inteface)
- single file headers from other projects go in include root
2020-03-29 19:53:29 +02:00
anabate123
2bfa946244 Added more speeds to Celeron (Slot 1/Socket 370)
What would preliminary Mendocino emulation be without the remaining speeds?
2020-03-26 16:59:43 -04:00
nerd73
51bbebbfa3 Changes to the IBM 386/486 and RapidCAD CPUs
- Disabled the 'is486' flag and moved them to 386 timings
- Disabled cache on startup, enable-able later
- RapidCAD fixes (permanently disable L1, correct EDX reset)
2020-03-25 18:02:25 -06:00
tiseno100
b1a421a2e9 Incorrect Encoding. Fixed 2020-03-25 12:31:54 +02:00
tiseno100
1f6d05f637 Added the Packard Bell Bora Pro + Celeron changes
Now Slot1 motherboards can access the Celeron processors at the Intel/PGA370 category
Added the Packard Bell Bora Pro. A 440ZX based AMI board. It's just a MSI 6168 with the AMI PB OEM BIOS slapped in it. It reports excessive amounts of RAM and also looks for an SDRAM serial(which is not a huge deal).

Roms can be found on the roms PR
2020-03-25 12:22:51 +02:00
Daniel Gurney
0c509fd551 Remove version tree-wide 2020-03-25 00:46:02 +02:00
OBattler
1ff55cdf10 Fixed the table of the 486's. 2020-03-23 23:41:20 +01:00
nerd73
c007121062 Merge branch 'temp' into temp 2020-03-23 16:06:32 -06:00
OBattler
43f2bb849b Merge branch 'temp' into temp 2020-03-23 22:02:52 +01:00
OBattler
6219cbd31a Overdoze's 486 CPUID changes. 2020-03-23 21:14:34 +01:00
nerd73
172f85ad40 Implemented MSRs 2020-03-21 23:42:01 -06:00
tiseno100
0d945fbf47 Added the ECS P6BXT-A+ 2020-03-21 10:04:11 +02:00
nerd73
111d82fa0c Preliminary VIA Cyrix III emulation
This adds preliminary emulation of the first-gen Samuel core, used in the VIA Cyrix III CPU, at clock speeds from 66 to 700 MHz. This also moves the 440BX emulation out of the dev-branch.

Things working:
- CPUID
- Windows 98SE
- Timings seem identical between WinChip/W2's integer section and this

Things left to do:
- 3DNow on old dynarec
- Half-speed FPU (currently simulated with WinChip 1 timings instead of WinChip 2)
2020-03-01 15:06:35 -07:00
OBattler
ed6e8ffb77 Fixed CPUID's for low-clocked Klamath and Deschutes Pentium II's. 2020-03-01 00:48:32 +01:00
OBattler
490c04fcae Current WIP code. 2020-02-29 19:12:23 +01:00