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81 Commits

Author SHA1 Message Date
OBattler
62193ab259 Intel i4x0: Extended the old register 52h behavior to all 430FX, 430HX, 430VX, and 430TX machines. 2024-05-09 18:10:32 +02:00
OBattler
b0542322bf Fixed DRB DIMM splitting (AMI Apollo now boots with 8 MB RAM), and extended the MB500N workaround to MR BIOS'es as well. 2024-05-09 00:47:45 +02:00
OBattler
4fe7ee9675 Added a PC Partner MB500N specific workaround to the i4x0 cache control register write. 2024-05-08 23:44:43 +02:00
OBattler
955297b9c4 Removed excess logging from the Intel 4x0 chipset emulation. 2024-04-18 04:33:20 +02:00
OBattler
1e5800d548 Intel 420TX-430TX cache control fixes. 2024-04-18 03:54:42 +02:00
OBattler
485e73d4da Added the Gateway Tomahawk (430TX machine). 2024-01-21 01:55:05 +01:00
OBattler
7013949310 Made sure the dummy "None"/"Internal" devices never get initialized and fixed some PCI AGP bridge mess (including AGP-less 440BX/ZX/GX erroneously initializing the 440LX/EX AGP bridge), fixes #3696. 2023-10-14 06:45:45 +02:00
OBattler
c30d5d90b7 PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable. 2023-08-07 03:04:52 +02:00
Jasmine Iwanek
998cfe5cc8 Constification 2023-07-25 17:59:24 -04:00
Jasmine Iwanek
ee695e71f9 More sonarlint work 2023-07-25 17:59:22 -04:00
OBattler
33ff6b77e8 Part 4. 2023-07-12 00:37:51 +02:00
OBattler
20e771ad3a Part 2. 2023-07-12 00:32:21 +02:00
Jasmine Iwanek
922c4335ae Next round of sonarlint cleanups 2023-06-27 21:17:13 -04:00
Jasmine Iwanek
21adfd4d50 Next round of sonarlint cleanups 2023-06-26 18:28:13 -04:00
Jasmine Iwanek
6c1e4a8e2c Some code smell fixes from sonarlint 2023-05-15 19:25:56 -04:00
Jasmine Iwanek
bd75bc141a Header cleanups 
Tabs to spaces
Consistency
 2022-11-13 21:15:47 -05:00
Jasmine Iwanek
fab1632cee Fixes almost all the logging options which were previously broken 2022-10-27 11:23:10 -04:00
Jasmine Iwanek
3753a9f8b2 clang-format in src/chipset/ 2022-09-18 17:19:21 -04:00
Jasmine Iwanek
a75aa6f412 Expose agpgart_t (#2655) 2022-08-31 19:23:38 -03:00
Jasmine Iwanek
a52f0cca79 src/chipset 2022-03-13 09:21:08 -04:00
Jasmine Iwanek
4674756664 More newline and whitespace cleanups 2022-02-20 16:26:40 -05:00
OBattler
bd0287d16f Fixed DRAM row boundaries on Intel 430LX and 430NX. 2022-02-06 00:32:23 +01:00
Jess Lovelace
f18615ae87 refactored device_t and all declarations 2022-02-02 16:31:22 -05:00
RichardG867
0de137daf7 Merge branch 'master' of https://github.com/86Box/86Box into cleanup30 
# Conflicts:
#	src/include/86box/machine.h
#	src/machine/m_at_socket7.c
#	src/machine/machine_table.c
#	src/video/vid_tgui9440.c
#	src/win/win.c
 2021-11-14 13:45:37 -03:00
RichardG867
724accd167 Add AGP GART implementation 2021-11-10 21:14:54 -03:00
OBattler
b4b4c45976 Merge remote-tracking branch 'origin/master' into feature/machine_and_kb 2021-10-21 21:20:21 +02:00
OBattler
066deef986 The version of 440BX without AGP now has revision 0x03. 2021-10-21 21:20:00 +02:00
OBattler
820e9eede7 Merge remote-tracking branch 'origin/master' into feature/machine_and_kb 2021-10-21 21:18:44 +02:00
OBattler
85f810aa22 The Virtual PC 2007 machine now correctly uses the version of 440BX without AGP. 2021-10-21 21:18:20 +02:00
OBattler
1c2d1e702b Assorted changes and bugfixes and added the two IMS 8848 machines. 2021-10-09 17:37:09 +02:00
OBattler
29c8e36e6e Fixed miscellaneous bugs reported by Coverity. 2021-07-04 20:50:03 +02:00
OBattler
877cf20e01 Fixed DRB's on the Intel 420TX and 420ZX. 2021-04-17 04:54:33 +02:00
nerd73
8e3b09f323 Various 486 improvements 
- Added SL-Enhanced versions of Intel 486 CPUs and Enhanced AMD Am486DX2/DX4 CPUs
- Cleaned up the 486 CPU types and updated intel_4x0.c to reflect this
- Fixed some incorrect EDX reset and CPUID values
- Blacklisted non-SMM capable 486 CPUs on the Soyo 4SA2 motherboard
- Merged the non-OverDrive and OverDrive Intel DX4s because of further research confirming them to be functionally identical
- Removed SMM support on early 486 CPUs
 2021-04-15 21:38:03 -06:00
OBattler
3e5c2b88d5 The Intel 420TX and 420ZX chipsets now correctly have 57h as the SMRAM control register (identified by register write logging on the ASUS P/I-486SP3G) rather than 72h, fixes hangs and errors on the ASUS P/I-486SP3G. 2021-04-13 02:33:40 +02:00
OBattler
3074d5b845 Cleaned up excess header includes from the chipset files and the ALI M1487/1489 is now correctly implemented (still Dev branched as I have not committed the machine files yet). 2021-03-24 20:03:20 +01:00
RichardG867
0f80e956d5 Add PCI and AGP speed control to i4x0 and VIA northbridges 2021-03-14 19:43:25 -03:00
qeeg
b9dfd082e1 Fixes to legitimate issues Sonarcloud caught in our code 2021-02-04 16:10:53 -06:00
OBattler
d2ad8fce43 Fixes to ACPI and 4x0 - fixes the Freeway. 2020-11-17 22:17:51 +01:00
OBattler
0faf6692c9 WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED. 
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite;
Added device.c/h API to obtain name from the device_t struct;
Significant changes to win/win_settings.c to clean up the code a bit and fix bugs;
Ported all the CPU and AudioPCI commits from PCem;
Added an API call to allow ACPI soft power off to gracefully stop the emulator;
Removed the Siemens PCD-2L from the Dev branch because it now works;
Removed the Socket 5 HP Vectra from the Dev branch because it now works;
Fixed the Compaq Presario and the Micronics Spitfire;
Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470;
SMM fixes;
Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions;
Changed IDE reset period to match the specification, fixes #929;
The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset;
Added the Intel AN430TX but Dev branched because it does not work;
The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full);
Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types;
USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it);
Fixed NVR on the the SMC FDC37C932QF and APM variants;
A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX;
Some ACPI changes.
 2020-11-16 00:01:21 +01:00
OBattler
795a6017d2 PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy). 2020-10-14 23:15:01 +02:00
RichardG867
f459c676c4 PCI/AGP bridge support, part 2: now with VIA 2020-09-19 01:29:35 -03:00
RichardG867
3314bd4035 PCI/AGP bridge support, part 1 2020-09-19 00:56:12 -03:00
RichardG867
e1b07f2fee Change special 440BX VPC behavior to is_vpc 2020-07-25 12:28:13 -03:00
RichardG867
e8f2fb0915 Isolate 440BX special behavior to devbranch 2020-07-24 15:02:59 -03:00
RichardG867
763b61c469 Add special behavior for a reserved 440BX bus speed bit for the Virtual PC 2007 machine 2020-07-24 15:00:58 -03:00
OBattler
751e5962d7 Fixed the bus speed register on the 440BX. 2020-07-24 17:06:43 +02:00
OBattler
5a862e9551 Fixed 440GX ID without AGP and the FDC now causes the CPU to run the timers on MSR read when the recompiler is used. 2020-07-09 19:28:47 +02:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
RichardG867
2553dbce8f Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD 2020-06-26 21:03:46 -03:00
RichardG867
93b909fe59 Merge branch 'master' of https://github.com/86Box/86Box 2020-06-26 18:05:57 -03:00