claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3,208 Commits 1 Branch 0 Tags
98b57912b31e25e5eb601569f3b3bc98a9615d07
Commit Graph

24 Commits

Author SHA1 Message Date
nerd73
3f0adb5211 Add the AMI Excalibur, a VLB OPTi 596/597 machine. 
Also adds emulation of the OPTi 5x7 chipset, and introduces a clock divider for VLB on 64-bit bus systems.
 2020-06-05 10:22:59 -06:00
nerd73
5596855871 Improved EBL_CR_POWERON MSR 
Improves emulation of the EBL_CR_POWERON MSR on Intel P6 and VIA C3 CPUs. Also makes a fix to a logging bug.
 2020-05-30 21:02:23 -06:00
nerd73
eebdcf85cb Made writing to MSR 0x8B GPF on Intel Pentium/Pentium MMX 
Windows Vista now (correctly) no longer works on these CPUs. IDT WinChip, AMD K6, VIA Cyrix III, and Intel P6 family CPUs are not affected.
 2020-05-17 19:28:40 -06:00
OBattler
23739b3dc6 Some CPU fixes, fixes #736. 2020-05-06 00:22:21 +02:00
OBattler
0570e21f0f Applied Ryuzaki's Media menu patch, fixed a bug in cpu.c reported by ms. person, fixed bugs (and added a workaround for the Windows 2000 PCnet problems) to mem.c, and added a network packet queue to cap network speed (and do the actual rx poll in the main thread instead) for more stability, also some ES1371 fixes (but not enough to make it work on Linux). 2020-04-29 23:39:54 +02:00
OBattler
70862a3c25 Added dmmy support for MSR 0x179 for Debian 10. 2020-04-21 19:24:00 +02:00
OBattler
600bb09f17 Added PS/2 Intel AMI keyboard controller type that always returns bit 6 of the input port as 1, fixes Intel Advanced/EV and Advanced/ZP SMM errors (with high-low beeps), and also IDE not found error behavior to fix IDE with some i686 BIOS'es. 2020-04-18 18:03:02 +02:00
OBattler
275dd5a2f7 ACPI, SMM, and PIIX fixes, fixes quite a few boards, also fixed the Via Apollo series northbridge ID's, some CPU instructions on both 808x and 286+, and added SMM to 486's (Intel and AMD), WinChip and WinChip 2, and VIA Cyrix III, also removed the TC430HX and the Toshiba machine from the Dev branch. 2020-04-16 21:56:19 +02:00
OBattler
61f0ae7954 Better ACPI implementation (currently only on PIIX4/PIIX4E/SMSC southbridges), finished the SMSC southbridge (but the Atrend BIOS still hangs, need to figure out why), and fixed Tandy EEPROM saving. 2020-04-13 20:01:47 +02:00
OBattler
d75e901a83 Moved the Intel i686 CPU's and related machines out of the Dev branch. 2020-04-10 20:01:26 +02:00
OBattler
2a0b3eb9c5 Added PAE, ported K6, P6, and WinChip 2 timings to the old recompiler, added a bunch of CPU's to the old recompiler, done some x87 fixes for both recompilers, added PAE, and fixed root directory entries for single-sided 5.25" DD floppies in the New Floppy Image dialog. 2020-04-10 01:08:52 +02:00
OBattler
7b93842881 Merge pull request #675 from driver1998/cr0 
Dynarec: Move CR0 into cpu_state
 2020-04-07 11:34:17 +02:00
GH Cao
d632f1dac9 Dynarec: Move CR0 into cpu_state 
Some dynarec backends (x86-64, arm64) expect the offset between cpu_state and CR0 to within a certain limit, otherwise they crashes (e.g: "host_x86_MOV64_REG_ABS - out of range").
Move CR0 to the end of cpu_state, make sure the offset is within limit.

Helps NT4 and Win95 with dynarec on.
 2020-04-07 17:02:34 +08:00
nerd73
312b96a897 Hacky P6 timing model based off K6 timings 2020-04-06 22:44:26 -06:00
OBattler
b8b198a56a Fixed SMM, overhauled the emulation of the VIA northbridges, and added the Via Apollo VP3. 2020-04-01 08:59:29 +02:00
nerd73
925f1f3784 Add MTRR CPUID bit and clean up VIA C3's CPUID feature bits. 2020-03-31 17:39:55 -06:00
David Hrdlička
a505894a10 Move all include files to src/include 
- 86Box's own headers go to /86box
- munt's public interface goes to /mt32emu
- all slirp headers go to /slirp (might want to consider using only its public inteface)
- single file headers from other projects go in include root
 2020-03-29 19:53:29 +02:00
nerd73
51bbebbfa3 Changes to the IBM 386/486 and RapidCAD CPUs 
- Disabled the 'is486' flag and moved them to 386 timings
- Disabled cache on startup, enable-able later
- RapidCAD fixes (permanently disable L1, correct EDX reset)
 2020-03-25 18:02:25 -06:00
Daniel Gurney
0c509fd551 Remove version tree-wide 2020-03-25 00:46:02 +02:00
nerd73
169bd9bdab Make everything compile correctly 
Everything should compile fine now.
 2020-03-23 13:05:44 -06:00
nerd73
1ab21acd20 Interpreter-only 3DNow for old dynarec 2020-03-22 19:59:01 -06:00
nerd73
172f85ad40 Implemented MSRs 2020-03-21 23:42:01 -06:00
nerd73
111d82fa0c Preliminary VIA Cyrix III emulation 
This adds preliminary emulation of the first-gen Samuel core, used in the VIA Cyrix III CPU, at clock speeds from 66 to 700 MHz. This also moves the 440BX emulation out of the dev-branch.

Things working:
- CPUID
- Windows 98SE
- Timings seem identical between WinChip/W2's integer section and this

Things left to do:
- 3DNow on old dynarec
- Half-speed FPU (currently simulated with WinChip 1 timings instead of WinChip 2)
 2020-03-01 15:06:35 -07:00
OBattler
490c04fcae Current WIP code. 2020-02-29 19:12:23 +01:00