- Renamed `cpp11_thread.cpp` to `thread.cpp`
- Removed features that are only supported by Win32 threads (`thread_wait` with timeout and mutex with spinlock)
- Fixed formatting in `thread.cpp`
Added the AT&T 2xc498 Precision RAMDAC.
Added 1MB configurations to the Cirrus Logic GD5434 as well as re-organized the memory size options of the other Cirrus cards.
Separated the et4000w32/i blitter from the standard et4000w32p blitter and properly implemented the X/Y Count route.
Added several Diamond Cirrus cards.
Added Number Nine S3 cards (868 and 968-based).
Fixed the WD90c30 1MB modes.
Re-organized the video card names.
Bit 1 is of 0x3DA (read only) is apparently required to make the OS/2 Tseng ET4000W32/i drivers work fine, fixes hangs upon reaching the GUI with said drivers.
Avoid division by zero in the blitter of the ET4000W32/i under OS/2.
Video changes (PVGA):
Fixes mode changes of the PVGA1a, including the built-in video card of the Amstrad 2086/3086.
Improved the banking of the ATI 28800-5 cards (VGA Charger and VGA Wonder XL).
Improved the skew and horizontal display of some of the ET4000W32P cards as well as the cursor.
Made the Oak OTI 077 and PVGA WD90c30 cards use the Sierra 11487 (actually a clone is used in the real cards).
For the WD90c30, changed the way the hack is involved.
Reverted some changes of the S3 Vision/Trio that originally made glitches, now the glitches are gone and the accelerator renders fine.
Re-organized the Sierra 1148x RAMDAC's and added the 11486 (Mark 1).
MCA SVGA cards use the full 32-bit mapping.
Properly fixed text/graphics mode of the S3 pre-ViRGE cards.
PIX TRANS cleanups.
Added a sanity check to banking, per bit 0 of CRTC31.
Initial implementation of Enhanced 4-bit mode.
911/924 chips use CRTC43 bit 3 for enabling 15/16bpp mode.
fb_only variable used correctly as of now (depending if on 4bit or 8bit+ modes).
S3 ViRGE changes part 2:
Made the Trio3D/2X AGP use the PCI_ADD_AGP part accordingly
RAMDAC changes:
Sierra 11483 and 11487 don't have an RS2 signal so the four times reading scheme of 0x3c6 is used instead, per documentation.
Fixed AT&T 49x bpp selection.
Other changes:
Fixed remaining rendering issues with the Radius SVGA HT209 card.
Added dword addressing to pix trans reads.
Added VRAM masking to the hardware cursor.
Properly fixed the FIFO slots.
Width set to 1024 by default in the 911 and 924 chips.
Added a timer to improve perfomance of the 3D engine.
Made the Trio3D/2X available for all.
Reserved bit 2 of CR33 is now always set to make sure Win95's Trio3d/2X drivers work along with a workaround for the memory size.
Added preliminary DMA bus master capabilities.
Reintroduced dword mode for chips before Trio64V+.
The Trio64V+ and Trio64V2 chips now have svga->fb_only (which is strongly required by the mapping and the modes) and packed_chain4 set, just like the ViRGE.
Rewritten non-threaded FIFO to be sure that it won't hang any OS (especially OS/2) and won't cause any more glitches on Windows 3.1 86x/96x drivers.
Fixed the decode mask of the Vision868 (8MB instead of 4MB).
Fixed 16bpp cursor using the MiroCRYSTAL 10SD specific drivers for OS/2 (including seamless Win-OS/2)
Fixed Chicago 73x (73f/g and 81)'s width/pitch in 15bpp mode using its built-in drivers at 800x600 using the 928.
Vastly improved implementation of the Short Stroke Vectors.
Removed threading for FIFO mode in the cards using the 964 chips and up.
Implementation of the non-threaded FIFO for cards using the 964 chips and up. Should fix most remaining wallpaper issues with those chips.
Improved recalctimings when 256+ mode Enhanced Mode is issued.
Added the MiroCRYSTAL 8S VLB card (805, SDAC).
