1. SVGA decode mask shouldn't be used in XGA native mode, fixes wrong locks in LFB access.
2. INMOS XGA only: more accurate emulation per INMOS G201 MCA/ISA manual, including the MMIO access and port 0x96, allowing full BIOS and MMIO access at the same time on 0xc0000.
8514/A changes:
1. Correct interlaced display resolution.
2. Added a limit to cursor coordinates.
3. Test/WIP features of the add-on Mach8 side (ATI 8514/A Ultra) such as configurable BIOS.
4. Made the CMD 5 of the acceleration (Polygon Boundary) more accurate per manual (as much as I could regarding the clipping).
Cirrus related:
1. Added SUBSYS PCI vendor/device ID of the 5480 (per manual).
IBM VGA:
1. Built-in/option rom-less VGA don't need the "available" flag.
ATI Mach8/32:
1. As with 8514/A, corrected interlaced display.
XGA-1/-2:
1. Moved the XGA R/W memory size tests out of the SVGA R/W routines to reflect the per card basis, although anything that uses its own SVGA mapping would call the tests there (such as Cirrus, Headland and ATI) when not accessing the LFB. This finally puts an end to the XGA MCA mapping enabling bugs.
2. Re-organized the ISA standalone and non-standalone (INMOS) sides of the chips so that they work properly and remove the FILE rom loading hack from init.
3. The Memory Mapped R/W sides now account for instance in their address range.
4. INMOS only: prevent any ROM address access to anything lower than 0xc8000 to not conflict with the main BIOS rom loading.
5. Fixed native pitch by using the correct register, this fixes non 1024x768 resolutions under NT.
6. More logs when enabled to see any future bugs.
1. Actually fix the remaining pinkish/reddish stuff in 32bpp modes properly (for real, especially OS/2 and possibly other stuff).
2. The Compare accel stuff is more sanitized.
3. When the BitBLT DY coordinates are negative, don't draw the pixels. This fixes some software cursor issues with OS/2's S3 3.03.xx drivers.
4. Reset the FIFO when the card is reset.
5. Indentation fixes (to be improved further however).
6. Implement bit 5 functionality of 0xBEE8 index 0xE (MULT_MISC) (and currently only in the Rectangle Fill command). This fixes missing text on I-O Data Vision968 specific drivers for Windows 3.10 Japanese (PC/AT compatible)
7. Moved the Streams engine out of the FIFO (like the ViRGE) as well as making all CRTC's of the Trio64V2 writable and SEQREGs from 0x10 onwards to make sure the Streams engine works properly.
8. Added a missing break from the RAMDAC read stuff.
9. Remove a leftover of PCem.
1. Going from screenshots of the Mach32 chips, they all have the ati18811-1 clock regardless of the bus type, whilst the Mach8 has an ati18812, which is actually a ati18811-0
2. Unbreak the NS3.1 Mach32 driver, ergo, don't block the LFB processing.
The so called "NT 3.5 font fix" on the Mach64 applies only to the Source Control reg with bits 2-3 set, but Solaris only sets bit 2 (without bit 3), so, don't align the source with bit 3 cleared. This fixes the garbled fonts under Solaris using said card.
Apparently the extended sequencer registers (>= 0x20) are required to have sane values on the STREAMS engine on GX2 and probably other chips in the ViRGE range.
1. ROM updated to 1.03.
2. Re-apply more fixes that were missed during the restructuring to be on par with PCem's speed.
3. Implemented Command DMA bus mastering required by Diamond Stealth 3D specific drivers (especially the GX2-based 4000).
4. Some indentation fixes.
1. TVP3026: disable lut mapping on 24bpp modes (mainly the S3 Vision968 drivers which use the TVP3026 ramdac).
2. S3 Vision968 (MiroVideo 40SV Ergo): Corrected 1280x1024 24bpp resolution.
3. ViRGE class: limit the FIFO entries in the bitblt regs to less than 16 entries and make the Image Transfers FIFO writes wraparound to 1 and reads to 0 (to allow at least a read to a write in the thread without hanging the entire emulator). Fixes Win3.1 PBRUSH colors while keeping performance on par with PCem.
