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a6bb71ea7a19c6c499cc2d441cedac34926cb412
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207 Commits

Author SHA1 Message Date
OBattler
f1f99aba89 Added NOHOOK option to the makefile, NOHOOK=y compiles without the keyboard hook. 2020-07-16 01:22:13 +02:00
OBattler
8e5fa10d0e Added the AMI386SX and OPEN_AT options to the makefile. 2020-07-12 19:40:48 +02:00
OBattler
23bc283e45 Added the HEDAKA option to the makefile. 2020-07-12 19:38:42 +02:00
OBattler
be0a681f31 Removed the PS/ValuePoint from the Dev branch and moved the other Socket 4 Dell there, and the PS/ValuePoint now uses the SMC FDC73C665 Super I/O chip and a PCI version of the PS/1 keyboard controller. 2020-07-12 01:04:41 +02:00
OBattler
72cfa4dcb8 Implemented the Intel 82091AA Super I/O chip and added the Packard Bell PB520R, closes #825. 2020-07-11 03:37:25 +02:00
OBattler
f696dc69ad Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine. 2020-07-08 04:24:25 +02:00
OBattler
39a46797d2 Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur. 2020-07-07 20:43:28 +02:00
RichardG867
8536f93dfc Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/cpu/cpu.c
 2020-07-06 19:00:31 -03:00
RichardG867
c1dd844747 Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/machine/machine_table.c
#	src/win/Makefile.mingw
 2020-07-06 18:47:50 -03:00
RichardG867
11114c97d2 Initial implementation of STPC chipsets and machines 2020-07-06 18:45:34 -03:00
nerd73
18368203ec Fix issues with Cyrix DX2/DX4 CPUs 
Fix some issues with the Cyrix DX2 & DX4 CPUs and restore the Cyrix 6x86 for dev-branch builds.
 2020-07-06 13:01:52 -06:00
nerd73
ff000b53cc actually make it work this time 2020-07-03 03:09:09 -06:00
Miran Grča
03932a329f Merge pull request #889 from tiseno100/master 
Added the RYC Leopard LX
 2020-07-03 04:41:05 +02:00
RichardG867
5d5883ac0d Merge branch 'master' of https://github.com/86Box/86Box 2020-07-02 21:42:52 -03:00
RichardG867
b043f1867b Genesys Logic GL518SM hardware monitor 2020-07-02 21:42:31 -03:00
tiseno100
525a6f0278 Added the RYC Leopard LX 
An interesting kind of 386DXish/486 kind of board. Uses the IBM 486SLC(only!) which is commonly found in PS/2 & PS/1 286 & 386 computers as an "upgrade" chip
 2020-07-02 22:10:36 +03:00
Miran Grča
8ebcfe766e Merge pull request #883 from amdk6/master 
Added various Dell machines
 2020-06-30 15:56:41 +02:00
OBattler
33a0cf53c4 Removed the "PS/1 Model 2133" Super I/O chip as it has been identified as a National Semiconductors PC87332 on a different set of ports, the PS/1 Model 2133 now uses that. 2020-06-30 15:49:47 +02:00
Gey Cunt
57d7982a53 Added various Dell machines 2020-06-30 16:15:48 +03:00
tiseno100
672b0bbef7 Deleted the Acer off the Makefile 
It's not needed anymore.
 2020-06-29 16:39:30 +03:00
tiseno100
cd840c4c02 Added the OPTi 895 in Makefile 2020-06-29 16:38:26 +03:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
TC1995
dd0180afcb Moved the IBM PS/1 Model 2133 out of dev branch. 
Added the VLSI VL82c480 chipset and the unknown sio that the PS/1 2133 EMEA 451 uses.
Added on-board Cirrus GD5426 video card
 2020-06-25 22:43:20 +02:00
TC1995
ba89af057c Added the Sierra SC11483 and SC11487 ramdac's. 
Made the S3 911 use the SC11483 plus a few minor changes to the S3 code itself.
 2020-06-25 13:18:29 +02:00
nerd73
09ffa05f89 Improvements to the OPTi 597 machine. 
- Add emulation of the FDC37C661 Super I/O
- Fix Pentium VLB timing (was running VLB at 2x bus speed instead of 1/2 bus speed)
- Fix the cache register on the OPTi 5x7 chipset
- The actual minimum RAM amount is 2 MB, not 1 MB.
- Fix chipset naming consistency
 2020-06-23 15:04:10 -06:00
tiseno100
3235e27f9b Inject one more space to Makefile. Fixes warnings. 2020-06-23 17:24:02 +03:00
tiseno100
f29e48d2d7 Restored the Intel 82335 chipset 
Restored the old Intel 82335 code remnant of the PCem-X era.
 2020-06-23 14:00:34 +03:00
tiseno100
295499eb85 Implemented the AMD 640 chipset 2020-06-22 11:09:11 +03:00
OBattler
d2dbf49e3c Added the Catalyst 28F010 Flash chip needed by the ASUS P5MP3, fixed a memory leak in the Intel Flash close code (it was not free'ing dev->array), and unified all the flash chip header files into one single flash.h. 2020-06-21 03:58:32 +02:00
TC1995
465789bd5c Fixed the fix 3 (grr). 2020-06-16 16:44:25 +02:00
OBattler
6d888cf869 Merge pull request #809 from nerd73/master 
Preliminary port of PCem's FPU timing emulation
 2020-06-15 17:12:08 +02:00
OBattler
6c6cae0965 Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged). 2020-06-15 17:08:42 +02:00
nerd73
a4d33513e4 Preliminary port of PCem's FPU timing emulation 2020-06-15 04:11:12 -06:00
OBattler
8837d5d882 Implemented the National Semiconductors PC87307, PC87309, PC87332, and PC97307 Super I/O chips, fixed a number of bugs, and removed two machines from the Dev branch due to them now having the correct Super I/O chips. 2020-06-14 21:59:45 +02:00
OBattler
ca55e2a12a More reorganization and finally merged the two makefiles. 2020-06-13 12:32:09 +02:00
OBattler
60ba71cb4b Renamed the three CPU folders to their final names. 2020-06-13 10:54:05 +02:00
OBattler
cfea8c4b64 Removed the USB variable from the makefile as it's no longer needed and only causes confusion. 2020-06-13 10:28:58 +02:00
OBattler
9c6f0d806e A slight reorganization of the source tree and fixed a warning in disk/mo.c. 2020-06-13 10:17:57 +02:00
OBattler
92a1425896 Implemented the Intel 420EX combined northbridge and southbridge, added the ASUS PVI-486AP4, and overhauled SMRAM handling (which also implements some previously missing extended SMRAM features of the 440BX+ and VIA Apollo series of chipsets). 2020-06-12 23:29:12 +02:00
RichardG867
f65b51b0f3 MPS table patcher for the ASUS P/I-P65UP5 2020-06-07 16:47:16 -03:00
RichardG867
aa4028aaff Revert "Merge branch 'master' of https://github.com/86Box/86Box" 
This reverts commit 7a4bddab3c, reversing
changes made to 416d4f673d.
 2020-06-07 15:52:45 -03:00
RichardG867
2ff06457d5 Hardware monitor refactoring, part 2 2020-05-18 22:54:59 -03:00
RichardG867
fe4ff767a1 Hardware monitor refactoring 2020-05-18 00:13:00 -03:00
OBattler
f46181db78 Several fixes - the MR BIOS'es now work on the recompiler (thank you, port EBh!), so they have been moved out of the Dev branch. 2020-05-13 03:43:02 +02:00
tiseno100
82b73e7941 SuperMicro WinBios 440LX & 440BX + Slot 2 440GX bringup 2020-05-12 19:33:26 +03:00
OBattler
241ad90b54 Got rid of a lot of incorrect variable declaration and missing extern's, 86Box now successfully links when compiled with GCC 10.x. 2020-05-12 13:36:47 +02:00
OBattler
3dd3396a2c Backported the codegen_accumulate functionality to the old recompiler, so Windows 98 first edition on i686 CPU's can stay fixed without i686 timings getting messed up. 2020-05-06 03:41:46 +02:00
OBattler
9c6cfc9a15 Optimized builds are now compiled with -fp-contact=fast for a slight performance improvement. 2020-05-06 00:27:05 +02:00
David Hrdlička
c728ece0ee win: Start splitting menu code from win_stbar.c 2020-04-26 21:03:31 +02:00
tiseno100
73b51bf573 Dev branch all machines with missing SIO chips + added the VS440FX 
This board returns D4 POST with no output. Needs further examination. Meant for the future PC87307 implementation.

Also all boards that miss their SIO chips got Dev Branched just in case 2.10 gets released while some miss their SIO.
 2020-04-25 18:59:37 +03:00