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85 Commits

Author SHA1 Message Date
Miran Grča
56098700d1 Merge pull request #882 from nerd73/pythonfix 
Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
 2020-06-30 15:56:29 +02:00
OBattler
81d178e9f6 Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip. 2020-06-30 15:37:07 +02:00
nerd73
546f0a83e7 Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset 2020-06-29 22:06:27 -06:00
OBattler
13e8d9c923 Fixed Shadow RAM handling for all OPTi 486 chipsets. 2020-06-30 03:24:06 +02:00
OBattler
9402f98a3b Rewrote the OPTi 82C495 emulation, added the OPTi 82C493, did some changes to the 82C8xx, and updated Makefile.local. 2020-06-30 00:34:49 +02:00
OBattler
a4301708da Added the OPTi 802G device (the 802G and 895 are register-identical), and added port 23h to the OPTi 8xx'es. 2020-06-29 18:44:20 +02:00
OBattler
4a8aa601b6 Fixed (and improved) the OPTi 895 chipset implementation. 2020-06-29 18:13:14 +02:00
tiseno100
388825377c Implemented the OPTi 895 
Similar the OPTi 495 & 802G. It's a 486 ISA/VLB chipset used by many known boards. One being the PB450.
 2020-06-29 16:26:18 +03:00
OBattler
5c1f947122 The VLSI VL82C480 chipset now has Port 92h, fixes the IBM PS/1 model 2133. 2020-06-29 14:33:12 +02:00
OBattler
014552f235 Fixes to SiS 496/497 and W83787F. 2020-06-29 04:32:30 +02:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
RichardG867
aea5461255 Implement DRB locking for VIA Apollo chipsets 2020-06-26 22:05:32 -03:00
RichardG867
2553dbce8f Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD 2020-06-26 21:03:46 -03:00
RichardG867
93b909fe59 Merge branch 'master' of https://github.com/86Box/86Box 2020-06-26 18:05:57 -03:00
RichardG867
5115214d01 DRB locking implementation 2020-06-26 18:05:27 -03:00
TC1995
dd0180afcb Moved the IBM PS/1 Model 2133 out of dev branch. 
Added the VLSI VL82c480 chipset and the unknown sio that the PS/1 2133 EMEA 451 uses.
Added on-board Cirrus GD5426 video card
 2020-06-25 22:43:20 +02:00
nerd73
09ffa05f89 Improvements to the OPTi 597 machine. 
- Add emulation of the FDC37C661 Super I/O
- Fix Pentium VLB timing (was running VLB at 2x bus speed instead of 1/2 bus speed)
- Fix the cache register on the OPTi 5x7 chipset
- The actual minimum RAM amount is 2 MB, not 1 MB.
- Fix chipset naming consistency
 2020-06-23 15:04:10 -06:00
tiseno100
a369dfa12d Use the correct UNIX encoding on the i82335 
For some reason it was CR LF
 2020-06-23 17:20:22 +03:00
tiseno100
f29e48d2d7 Restored the Intel 82335 chipset 
Restored the old Intel 82335 code remnant of the PCem-X era.
 2020-06-23 14:00:34 +03:00
tiseno100
295499eb85 Implemented the AMD 640 chipset 2020-06-22 11:09:11 +03:00
OBattler
2655873162 A number of PCI fixes and P5MP3 corrections. 2020-06-21 05:23:49 +02:00
TC1995
2831d7a879 Ported the latest cs8230 patch from greatpsycho. 2020-06-17 23:47:37 +02:00
OBattler
7d4813aea7 PIIX now disables IDE on hard reset, fixes the AP440FX hard reset slowness. 2020-06-15 20:06:03 +02:00
OBattler
6c6cae0965 Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged). 2020-06-15 17:08:42 +02:00
OBattler
611dd62fab Some chipset extended SMRAM-related clean-ups and SMM-supporting chipsets now correctly set shadow RAM states for SMM mode in addition to non-SMM mode, fixes Windows 98 SE hanging in a SMI# handler. 2020-06-14 14:50:30 +02:00
OBattler
ca55e2a12a More reorganization and finally merged the two makefiles. 2020-06-13 12:32:09 +02:00
OBattler
ebe07c7e82 Moved the two (unused) Intel 386 chipset files to chipset/. 2020-06-13 10:27:07 +02:00
OBattler
9c6f0d806e A slight reorganization of the source tree and fixed a warning in disk/mo.c. 2020-06-13 10:17:57 +02:00
OBattler
92a1425896 Implemented the Intel 420EX combined northbridge and southbridge, added the ASUS PVI-486AP4, and overhauled SMRAM handling (which also implements some previously missing extended SMRAM features of the 440BX+ and VIA Apollo series of chipsets). 2020-06-12 23:29:12 +02:00
OBattler
563a432b7e Merge pull request #791 from richardg867/master 
MPS table patcher for the ASUS P/I-P65UP5
 2020-06-08 23:50:18 +02:00
tiseno100
6bbceab8a4 Added the 440GX 
Not that perfect implementation. But works to the most part
 2020-06-08 23:28:56 +03:00
RichardG867
151d8d486a Small indentation and header fixes 2020-06-07 16:03:15 -03:00
RichardG867
aa4028aaff Revert "Merge branch 'master' of https://github.com/86Box/86Box" 
This reverts commit 7a4bddab3c, reversing
changes made to 416d4f673d.
 2020-06-07 15:52:45 -03:00
OBattler
e109a59a56 Removed excess logging from the SiS Rabbit chipset. 2020-06-07 01:56:35 +02:00
OBattler
5f64a6f851 SiS Rabbit (85c310) shadow RAM handling rewrite (fixes IDE, same as on the ACC chipset) and fixed a warning in the AD1848 code. 2020-06-07 01:54:19 +02:00
tiseno100
66c4ea194d Added the "fixed" Rabbit code 2020-06-06 07:50:11 +03:00
OBattler
df72311429 Merge branch 'master' of https://github.com/86Box/86Box 2020-06-06 05:47:29 +02:00
OBattler
ca3ef2bc5b Fixed ACC2168 chipset shadow RAM state setting because it was completely wrong, fixes IDE problems (yes, really) on the AMI 386DX Clone. 2020-06-06 05:47:07 +02:00
tiseno100
0af3f90c8f Added the 440EX 2020-06-05 23:12:36 +03:00
OBattler
b4fee61fa2 Merge pull request #782 from nerd73/master 
Add the AMI Excalibur, a VLB OPTi 596/597 machine.
 2020-06-05 19:20:45 +02:00
tiseno100
b04908f2a1 440LX implementation 2020-06-05 19:30:39 +03:00
nerd73
51572530ff Remove waitstates from register 02. 2020-06-05 10:28:03 -06:00
nerd73
3f0adb5211 Add the AMI Excalibur, a VLB OPTi 596/597 machine. 
Also adds emulation of the OPTi 5x7 chipset, and introduces a clock divider for VLB on 64-bit bus systems.
 2020-06-05 10:22:59 -06:00
tiseno100
c9003894ed Few minor changes on the VPX 2020-05-07 17:51:53 +03:00
tiseno100
ff29e04490 Added the missing 2 RW bitfields on command. 2020-04-29 11:39:25 +03:00
tiseno100
570034cb09 Improved the VIA VPX code 
Moved host bridge write code via_vpx_write.
Default registers are now on via_vpx_init.
Read only registers are hardcoded.
 2020-04-29 10:50:53 +03:00
tiseno100
ea357593bd removed the function switch off write 2020-04-17 12:41:27 +03:00
tiseno100
16c1584412 Apollo VPX bringup 
This commit brings Apollo VPX emulation on 86Box. It includes the Zida Tomato TX100 board. Meant mostly to check issues at WinBioses
 2020-04-17 12:34:39 +03:00
OBattler
275dd5a2f7 ACPI, SMM, and PIIX fixes, fixes quite a few boards, also fixed the Via Apollo series northbridge ID's, some CPU instructions on both 808x and 286+, and added SMM to 486's (Intel and AMD), WinChip and WinChip 2, and VIA Cyrix III, also removed the TC430HX and the Toshiba machine from the Dev branch. 2020-04-16 21:56:19 +02:00
OBattler
61f0ae7954 Better ACPI implementation (currently only on PIIX4/PIIX4E/SMSC southbridges), finished the SMSC southbridge (but the Atrend BIOS still hangs, need to figure out why), and fixed Tandy EEPROM saving. 2020-04-13 20:01:47 +02:00