OBattler
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c30d5d90b7
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PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
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2023-08-07 03:04:52 +02:00 |
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Jasmine Iwanek
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998cfe5cc8
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Constification
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2023-07-25 17:59:24 -04:00 |
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Jasmine Iwanek
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ee695e71f9
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More sonarlint work
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2023-07-25 17:59:22 -04:00 |
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Jasmine Iwanek
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922c4335ae
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Next round of sonarlint cleanups
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2023-06-27 21:17:13 -04:00 |
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Jasmine Iwanek
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21adfd4d50
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Next round of sonarlint cleanups
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2023-06-26 18:28:13 -04:00 |
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OBattler
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ecb8091d41
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Fixed Cacodemon345's OHCI mess and implemented proper OHCI IRQ updating, fixes the Gigabyte GA-5AX POST.
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2023-05-07 02:53:04 +02:00 |
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Cacodemon345
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3f461afeeb
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usb: start hooking up USB interrupts to chipsets
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2023-05-05 00:28:08 +06:00 |
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OBattler
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8fca57aa79
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Universalize the keyboard and mouse latches again, fixes #3280.
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2023-05-01 01:35:16 +02:00 |
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OBattler
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ef17003f1b
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Fixed the "minor bug fix" in the AT / PS/2 keyboard controller, reworked PS/2 keyboard controller IRQ latches, and correctly disabled memory top remaps if there's more than (16 MB - remap size) RAM (fixes segmentation faults on some machines with 16+ MB of RAM).
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2023-04-11 23:21:52 +02:00 |
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Jasmine Iwanek
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bd75bc141a
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Header cleanups
Tabs to spaces
Consistency
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2022-11-13 21:15:47 -05:00 |
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Jasmine Iwanek
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fab1632cee
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Fixes almost all the logging options which were previously broken
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2022-10-27 11:23:10 -04:00 |
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Jasmine Iwanek
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3753a9f8b2
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clang-format in src/chipset/
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2022-09-18 17:19:21 -04:00 |
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OBattler
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f6fef765d7
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Chipsets.
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2022-07-16 02:58:37 +02:00 |
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Jasmine Iwanek
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a52f0cca79
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src/chipset
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2022-03-13 09:21:08 -04:00 |
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Jess Lovelace
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f18615ae87
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refactored device_t and all declarations
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2022-02-02 16:31:22 -05:00 |
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Alexander Babikov
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0208c7560f
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Fix incorrectly set 7.16 MHz clock speeds on some chipsets
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2021-04-26 04:21:29 +05:00 |
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Panagiotis
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ba92f1df34
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Finalize the SiS Pentiums
- Implemented the SiS 5511
- The SiS 5571 can safely go off Dev Branch now
- Few fixes on the SiS 5598
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2021-04-25 13:23:41 +03:00 |
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Panagiotis
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5e24a55067
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Minor changes for the Internal IDE of the SiS 5571
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2021-03-31 14:30:10 +03:00 |
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Panagiotis
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e9c589e7bc
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SiS 5571 can now configure the ISA bus clock
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2021-03-31 13:52:25 +03:00 |
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Panagiotis
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88165ae918
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Fixes and Improvements on the SiS 5571
- SMI is now properly provoked
- Removed default methods for registers
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2021-03-31 13:26:16 +03:00 |
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Panagiotis
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67290bcac8
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Minor bugfixes on the SiS 5571
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2021-01-24 15:34:24 +02:00 |
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Panagiotis
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9ed2456ebb
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Minor changes on the ALi's & few other chipsets.
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2021-01-13 16:13:07 +02:00 |
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Panagiotis
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d8b695b76c
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The SiS 5571 IDE & USB handlers are now accessed when they're actually needed
Fixes massive performance slowdowns.
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2020-12-24 20:11:21 +02:00 |
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Panagiotis
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68e1b3fd99
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Few fixes for the SiS 5571
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2020-12-23 18:02:22 +02:00 |
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Panagiotis
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59bbfdd019
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SiS 5571 implementation
A Socket 7 highly integrated chipset by SiS. Best performer for the Cyrix 6x86 CPUs of the time
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2020-12-23 18:00:53 +02:00 |
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