4 Commits

Author	SHA1	Message	Date
OBattler	4d676678e7	Removed an excess log line from the SDAC code.	2016-07-23 17:53:30 +02:00
OBattler	8fa2d256df	Fixed SDAC BPP modes and VCLK timings according to the datasheet.	2016-07-23 17:49:41 +02:00
OBattler	f41bbb6ba8	Added emulation of Cardex ET4000/W32p with ICS/SDAC RAMDAC; ... Fixed ET4000/W32p clock (for non-Diamond variants) and banking extension; Brought the code on par with the mainline; Fixed names of the two Cardex ET4000/W32p variants per the BIOS'es; Brought ET4000AX unknown RAMDAC back in line with the mainline (reverted bogus "fix" by Win9xFan); Made 15bpp and 16bpp colors more accurate.	2016-07-23 01:48:47 +02:00
OBattler	fd2a5bc9f5	Initial submission of the PCem-Experimental source code.	2016-06-26 00:34:39 +02:00