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105 Commits

Author SHA1 Message Date
OBattler
f696dc69ad Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine. 2020-07-08 04:24:25 +02:00
RichardG867
a1f267da72 Fix PCI IDs again 2020-07-07 17:07:08 -03:00
RichardG867
d8e3e44f59 Fix STPC PCI IDs again 2020-07-07 17:00:40 -03:00
RichardG867
1b637fbb77 Merge branch 'master' of https://github.com/86Box/86Box 2020-07-07 15:57:58 -03:00
OBattler
39a46797d2 Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur. 2020-07-07 20:43:28 +02:00
RichardG867
5e18163b2e Fix STPC CPU identification 
Let port 22h/23h registers >= 0xc0 fall through to the Cyrix port 22h/23h code in cpu.c
 2020-07-07 15:38:34 -03:00
RichardG867
f7e7359d2f Merge branch 'master' of https://github.com/86Box/86Box 2020-07-07 13:26:49 -03:00
RichardG867
5b0e29d0ff STPC improvements 2020-07-07 13:25:17 -03:00
tiseno100
91d7dd149a Commented the OPTi 283 logging code back 2020-07-07 16:40:07 +03:00
tiseno100
2137c4ea85 Fixed a minor mistake 2020-07-07 16:38:10 +03:00
tiseno100
ebe7f1cdf3 Rewrote the OPTi 283 shadowing 
Now it'll pass a check to see if we are write protecting or have write enabled.
 2020-07-07 16:36:44 +03:00
RichardG867
710796a180 Add ITOX STAR, a STPC Client machine with hardware monitoring and AMIBIOS 6 2020-07-06 21:12:09 -03:00
RichardG867
1ed6143f02 Implement STPC IDE 
Note that only the AR-B1479 has two IDE channels available on the board.
 2020-07-06 20:24:24 -03:00
RichardG867
c1dd844747 Merge branch 'master' of https://github.com/86Box/86Box 
# Conflicts:
#	src/machine/machine_table.c
#	src/win/Makefile.mingw
 2020-07-06 18:47:50 -03:00
RichardG867
11114c97d2 Initial implementation of STPC chipsets and machines 2020-07-06 18:45:34 -03:00
nerd73
2b06dbc10b Merge branch 'opti291' of https://github.com/nerd73/86Box into opti291 2020-07-03 03:09:48 -06:00
nerd73
ff000b53cc actually make it work this time 2020-07-03 03:09:09 -06:00
nerd73
6a9fa51d78 fix header 2020-07-03 00:24:48 -06:00
nerd73
5b260dbfd4 Add a 386SX Award v4.20 machine 
As well as a basic implementation of the OPTi 291 chipset that it uses.
 2020-07-03 00:18:16 -06:00
tiseno100
525a6f0278 Added the RYC Leopard LX 
An interesting kind of 386DXish/486 kind of board. Uses the IBM 486SLC(only!) which is commonly found in PS/2 & PS/1 286 & 386 computers as an "upgrade" chip
 2020-07-02 22:10:36 +03:00
Miran Grča
56098700d1 Merge pull request #882 from nerd73/pythonfix 
Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
 2020-06-30 15:56:29 +02:00
OBattler
81d178e9f6 Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip. 2020-06-30 15:37:07 +02:00
nerd73
546f0a83e7 Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset 2020-06-29 22:06:27 -06:00
OBattler
13e8d9c923 Fixed Shadow RAM handling for all OPTi 486 chipsets. 2020-06-30 03:24:06 +02:00
OBattler
9402f98a3b Rewrote the OPTi 82C495 emulation, added the OPTi 82C493, did some changes to the 82C8xx, and updated Makefile.local. 2020-06-30 00:34:49 +02:00
OBattler
a4301708da Added the OPTi 802G device (the 802G and 895 are register-identical), and added port 23h to the OPTi 8xx'es. 2020-06-29 18:44:20 +02:00
OBattler
4a8aa601b6 Fixed (and improved) the OPTi 895 chipset implementation. 2020-06-29 18:13:14 +02:00
tiseno100
388825377c Implemented the OPTi 895 
Similar the OPTi 495 & 802G. It's a 486 ISA/VLB chipset used by many known boards. One being the PB450.
 2020-06-29 16:26:18 +03:00
OBattler
5c1f947122 The VLSI VL82C480 chipset now has Port 92h, fixes the IBM PS/1 model 2133. 2020-06-29 14:33:12 +02:00
OBattler
014552f235 Fixes to SiS 496/497 and W83787F. 2020-06-29 04:32:30 +02:00
OBattler
96228bc41d Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there. 2020-06-29 01:10:20 +02:00
RichardG867
aea5461255 Implement DRB locking for VIA Apollo chipsets 2020-06-26 22:05:32 -03:00
RichardG867
2553dbce8f Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD 2020-06-26 21:03:46 -03:00
RichardG867
93b909fe59 Merge branch 'master' of https://github.com/86Box/86Box 2020-06-26 18:05:57 -03:00
RichardG867
5115214d01 DRB locking implementation 2020-06-26 18:05:27 -03:00
TC1995
dd0180afcb Moved the IBM PS/1 Model 2133 out of dev branch. 
Added the VLSI VL82c480 chipset and the unknown sio that the PS/1 2133 EMEA 451 uses.
Added on-board Cirrus GD5426 video card
 2020-06-25 22:43:20 +02:00
nerd73
09ffa05f89 Improvements to the OPTi 597 machine. 
- Add emulation of the FDC37C661 Super I/O
- Fix Pentium VLB timing (was running VLB at 2x bus speed instead of 1/2 bus speed)
- Fix the cache register on the OPTi 5x7 chipset
- The actual minimum RAM amount is 2 MB, not 1 MB.
- Fix chipset naming consistency
 2020-06-23 15:04:10 -06:00
tiseno100
a369dfa12d Use the correct UNIX encoding on the i82335 
For some reason it was CR LF
 2020-06-23 17:20:22 +03:00
tiseno100
f29e48d2d7 Restored the Intel 82335 chipset 
Restored the old Intel 82335 code remnant of the PCem-X era.
 2020-06-23 14:00:34 +03:00
tiseno100
295499eb85 Implemented the AMD 640 chipset 2020-06-22 11:09:11 +03:00
OBattler
2655873162 A number of PCI fixes and P5MP3 corrections. 2020-06-21 05:23:49 +02:00
TC1995
2831d7a879 Ported the latest cs8230 patch from greatpsycho. 2020-06-17 23:47:37 +02:00
OBattler
7d4813aea7 PIIX now disables IDE on hard reset, fixes the AP440FX hard reset slowness. 2020-06-15 20:06:03 +02:00
OBattler
6c6cae0965 Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged). 2020-06-15 17:08:42 +02:00
OBattler
611dd62fab Some chipset extended SMRAM-related clean-ups and SMM-supporting chipsets now correctly set shadow RAM states for SMM mode in addition to non-SMM mode, fixes Windows 98 SE hanging in a SMI# handler. 2020-06-14 14:50:30 +02:00
OBattler
ca55e2a12a More reorganization and finally merged the two makefiles. 2020-06-13 12:32:09 +02:00
OBattler
ebe07c7e82 Moved the two (unused) Intel 386 chipset files to chipset/. 2020-06-13 10:27:07 +02:00
OBattler
9c6f0d806e A slight reorganization of the source tree and fixed a warning in disk/mo.c. 2020-06-13 10:17:57 +02:00
OBattler
92a1425896 Implemented the Intel 420EX combined northbridge and southbridge, added the ASUS PVI-486AP4, and overhauled SMRAM handling (which also implements some previously missing extended SMRAM features of the 440BX+ and VIA Apollo series of chipsets). 2020-06-12 23:29:12 +02:00
OBattler
563a432b7e Merge pull request #791 from richardg867/master 
MPS table patcher for the ASUS P/I-P65UP5
 2020-06-08 23:50:18 +02:00