506 lines
17 KiB
C
506 lines
17 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ALi M1489 chipset.
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*
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*
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020-2021 Tiseno100.
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* Copyright 2020-2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/pic.h>
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#include <86box/pci.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/smram.h>
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#include <86box/chipset.h>
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#define DEFINE_SHADOW_PROCEDURE (((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | \
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((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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#ifdef ENABLE_ALI1489_LOG
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int ali1489_do_log = ENABLE_ALI1489_LOG;
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static void
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ali1489_log(const char *fmt, ...)
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{
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va_list ap;
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if (ali1489_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define ali1489_log(fmt, ...)
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#endif
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typedef struct ali1489_t {
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uint8_t index;
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uint8_t pci_slot;
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uint8_t regs[256];
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uint8_t pci_conf[256];
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port_92_t *port_92;
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smram_t *smram;
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} ali1489_t;
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static void
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ali1489_shadow_recalc(ali1489_t *dev)
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{
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shadowbios = shadowbios_write = 0;
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for (uint8_t i = 0; i < 8; i++) {
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if (dev->regs[0x13] & (1 << i)) {
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ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
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0xc0000 + (i << 14), 0xc3fff + (i << 14),
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!!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DEFINE_SHADOW_PROCEDURE);
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} else {
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ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xc0000 + (i << 14), 0xc3fff + (i << 14));
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DISABLED_SHADOW);
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}
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}
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for (uint8_t i = 0; i < 4; i++) {
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if (dev->regs[0x14] & (1 << i)) {
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ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
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0xe0000 + (i << 15), 0xe7fff + (i << 15),
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!!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
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mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DEFINE_SHADOW_PROCEDURE);
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shadowbios |= !!(dev->regs[0x14] & 0x10);
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shadowbios_write |= !!(dev->regs[0x14] & 0x20);
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} else {
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ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xe0000 + (i << 15), 0xe7fff + (i << 15));
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mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DISABLED_SHADOW);
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}
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}
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flushmmucache_nopc();
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}
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static void
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ali1489_smram_recalc(ali1489_t *dev)
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{
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/* The datasheet documents SMM behavior quite terribly.
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Everything were done according to the M1489 programming guide. */
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smram_disable(dev->smram);
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switch (dev->regs[0x19] & 0x30) {
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case 0x10:
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smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1);
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break;
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case 0x20:
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smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), 1);
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break;
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case 0x30:
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if ((dev->regs[0x35] & 0xc0) == 0x80)
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smram_enable(dev->smram, 0x68000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
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else
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smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
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break;
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default:
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break;
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}
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if ((dev->regs[0x19] & 0x31) == 0x11) {
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/* If SMRAM is enabled and bit 0 is set, code still goes to DRAM. */
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mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
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}
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}
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static void
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ali1489_defaults(ali1489_t *dev)
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{
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memset(dev->pci_conf, 0x00, 256);
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memset(dev->regs, 0x00, 256);
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/* PCI registers */
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dev->pci_conf[0x00] = 0xb9;
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x89;
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dev->pci_conf[0x03] = 0x14;
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dev->pci_conf[0x04] = 0x07;
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dev->pci_conf[0x07] = 0x04;
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dev->pci_conf[0x0b] = 0x06;
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/* ISA registers */
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dev->regs[0x01] = 0x0f;
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dev->regs[0x02] = 0x0f;
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dev->regs[0x10] = 0xf1;
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dev->regs[0x11] = 0xff;
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dev->regs[0x15] = 0x20;
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dev->regs[0x16] = 0x30;
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dev->regs[0x19] = 0x04;
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dev->regs[0x21] = 0x72;
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dev->regs[0x28] = 0x02;
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dev->regs[0x2b] = 0xdb;
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dev->regs[0x3c] = 0x03;
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dev->regs[0x3d] = 0x01;
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dev->regs[0x40] = 0x03;
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ali1489_shadow_recalc(dev);
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cpu_cache_int_enabled = 0;
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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ali1489_smram_recalc(dev);
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port_92_remove(dev->port_92);
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picintc(1 << 10);
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picintc(1 << 15);
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nmi = 0;
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smi_line = 0;
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in_smm = 0;
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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}
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static void
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ali1489_write(uint16_t addr, uint8_t val, void *priv)
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{
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ali1489_t *dev = (ali1489_t *) priv;
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uint8_t old;
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uint8_t irq;
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const uint8_t irq_array[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 };
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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/* Check if the configuration registers are unlocked */
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if (dev->regs[0x03] == 0xc5) {
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switch (dev->index) {
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case 0x03: /* Lock Register */
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case 0x10: /* DRAM Configuration Register I */
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case 0x11: /* DRAM Configuration Register II */
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case 0x12: /* ROM Function Register */
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dev->regs[dev->index] = val;
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break;
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case 0x13: /* Shadow Region Register */
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case 0x14: /* Shadow Control Register */
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if (dev->index == 0x14)
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dev->regs[dev->index] = (val & 0xbf);
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else
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dev->regs[dev->index] = val;
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ali1489_shadow_recalc(dev);
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ali1489_smram_recalc(dev);
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break;
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case 0x15: /* Cycle Check Point Control Register */
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dev->regs[dev->index] = (val & 0xf1);
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break;
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case 0x16: /* Cache Control Register I */
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dev->regs[dev->index] = val;
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cpu_cache_int_enabled = (val & 0x01);
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cpu_cache_ext_enabled = (val & 0x02);
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cpu_update_waitstates();
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break;
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case 0x17: /* Cache Control Register II */
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dev->regs[dev->index] = val;
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break;
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case 0x19: /* SMM Control Register */
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dev->regs[dev->index] = val;
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ali1489_smram_recalc(dev);
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break;
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case 0x1a: /* EDO DRAM Configuration Register */
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case 0x1b: /* DRAM Timing Control Register */
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dev->regs[dev->index] = val;
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break;
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case 0x1c: /* Memory Data Buffer Direction Control Register */
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dev->regs[dev->index] = val & 0x1f;
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break;
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case 0x1e: /* Linear Wrapped Burst Order Mode Control Register */
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dev->regs[dev->index] = (val & 0x40);
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break;
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case 0x20: /* CPU to PCI Buffer Control Register */
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dev->regs[dev->index] = val;
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break;
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case 0x21: /* DEVSELJ Check Point Setting Register */
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dev->regs[dev->index] = (val & 0xbb) | 0x04;
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break;
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case 0x22: /* PCI to CPU W/R Buffer Configuration Register */
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dev->regs[dev->index] = (val & 0xfd);
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break;
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case 0x25: /* GP/MEM Address Definition Register I */
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case 0x26: /* GP/MEM Address Definition Register II */
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case 0x27: /* GP/MEM Address Definition Register III */
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dev->regs[dev->index] = val;
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break;
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case 0x28: /* PCI Arbiter Control Register */
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dev->regs[dev->index] = val & 0x3f;
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break;
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case 0x29: /* System Clock Register */
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dev->regs[dev->index] = val;
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port_92_remove(dev->port_92);
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if (val & 0x10)
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port_92_add(dev->port_92);
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break;
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case 0x2a: /* I/O Recovery Register */
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dev->regs[dev->index] = val;
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break;
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case 0x2b: /* Turbo Function Register */
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dev->regs[dev->index] = (val & 0xbf) | 0x40;
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break;
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case 0x30: /* Power Management Unit Control Register */
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old = dev->regs[dev->index];
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dev->regs[dev->index] = val;
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if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) {
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switch (dev->regs[0x35] & 0x30) {
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case 0x00:
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smi_raise();
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break;
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case 0x10:
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nmi_raise();
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break;
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case 0x20:
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picint(1 << 15);
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break;
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case 0x30:
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picint(1 << 10);
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break;
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default:
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break;
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}
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dev->regs[0x35] |= 0x0e;
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} else if (!(val & 0x10))
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dev->regs[0x35] &= ~0x0f;
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break;
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case 0x31: /* Mode Timer Monitoring Events Selection Register I */
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case 0x32: /* Mode Timer Monitoring Events Selection Register II */
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case 0x33: /* SMI Triggered Events Selection Register I */
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case 0x34: /* SMI Triggered Events Selection Register II */
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dev->regs[dev->index] = val;
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break;
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case 0x35: /* SMI Status Register */
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dev->regs[dev->index] = (dev->regs[dev->index] & 0x0f) | (val & 0xf0);
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break;
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case 0x36: /* IRQ Channel Group Selected Control Register I */
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dev->regs[dev->index] = (val & 0xe5);
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break;
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case 0x37: /* IRQ Channel Group Selected Control Register II */
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dev->regs[dev->index] = (val & 0xef);
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break;
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case 0x38: /* DRQ Channel Selected Control Register */
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case 0x39: /* Mode Timer Setting Register */
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case 0x3a: /* Input_device Timer Setting Register */
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case 0x3b: /* GP/MEM Timer Setting Register */
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case 0x3c: /* LED Flash Control Register */
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dev->regs[dev->index] = val;
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break;
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case 0x3d: /* Miscellaneous Register I */
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dev->regs[dev->index] = (val & 0x07);
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break;
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case 0x40: /* Clock Generator Control Feature Register */
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dev->regs[dev->index] = (val & 0x3f);
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break;
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case 0x41: /* Power Control Output Register */
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dev->regs[dev->index] = val;
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break;
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case 0x42: /* PCI INTx Routing Table Mapping Register I */
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irq = irq_array[val & 0x0f];
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pci_set_irq_routing(PCI_INTA, (irq != 0) ? irq : PCI_IRQ_DISABLED);
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irq = irq_array[(val & 0xf0) >> 4];
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pci_set_irq_routing(PCI_INTB, (irq != 0) ? irq : PCI_IRQ_DISABLED);
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break;
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case 0x43: /* PCI INTx Routing Table Mapping Register II */
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irq = irq_array[val & 0x0f];
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pci_set_irq_routing(PCI_INTC, (irq != 0) ? irq : PCI_IRQ_DISABLED);
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irq = irq_array[(val & 0xf0) >> 4];
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pci_set_irq_routing(PCI_INTD, (irq != 0) ? irq : PCI_IRQ_DISABLED);
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break;
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case 0x44: /* PCI INTx Sensitivity Register */
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/* TODO: When doing the IRQ and PCI IRQ rewrite,
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bits 0 to 3 toggle edge/level output. */
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dev->regs[dev->index] = val;
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break;
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default:
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break;
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}
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if (dev->index != 0x03) {
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ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val);
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}
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} else if (dev->index == 0x03)
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dev->regs[dev->index] = val;
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break;
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default:
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break;
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}
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}
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static uint8_t
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ali1489_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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const ali1489_t *dev = (ali1489_t *) priv;
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switch (addr) {
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case 0x23:
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/* Avoid conflict with Cyrix CPU registers */
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if (((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix)
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ret = 0xff;
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else if (dev->index == 0x3f)
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ret = inb(0x70);
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else
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ret = dev->regs[dev->index];
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break;
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default:
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break;
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}
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ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret);
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return ret;
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}
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static void
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ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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{
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ali1489_t *dev = (ali1489_t *) priv;
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ali1489_log("M1489-PCI: dev->pci_conf[%02x] = %02x\n", addr, val);
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switch (addr) {
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/* Dummy PCI Config */
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case 0x04:
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dev->pci_conf[0x04] = val & 0x7f;
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break;
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/* Dummy PCI Status */
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case 0x07:
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dev->pci_conf[0x07] &= ~(val & 0xb8);
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break;
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default:
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break;
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}
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}
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static uint8_t
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ali1489_pci_read(UNUSED(int func), int addr, void *priv)
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{
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const ali1489_t *dev = (ali1489_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->pci_conf[addr];
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ali1489_log("M1489-PCI: dev->pci_conf[%02x] (%02x)\n", addr, ret);
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return ret;
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}
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static void
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ali1489_reset(void *priv)
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{
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ali1489_t *dev = (ali1489_t *) priv;
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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ali1489_defaults(dev);
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}
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static void
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ali1489_close(void *priv)
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{
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ali1489_t *dev = (ali1489_t *) priv;
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smram_del(dev->smram);
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free(dev);
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}
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static void *
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ali1489_init(UNUSED(const device_t *info))
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{
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ali1489_t *dev = (ali1489_t *) calloc(1, sizeof(ali1489_t));
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/* M1487/M1489
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22h Index Port
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23h Data Port */
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io_sethandler(0x0022, 0x0002, ali1489_read, NULL, NULL, ali1489_write, NULL, NULL, dev);
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/* Dummy M1489 PCI device */
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pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev, &dev->pci_slot);
|
|
|
|
device_add(&ide_ali1489_device);
|
|
|
|
dev->port_92 = device_add(&port_92_pci_device);
|
|
dev->smram = smram_add();
|
|
|
|
ali1489_defaults(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t ali1489_device = {
|
|
.name = "ALi M1489",
|
|
.internal_name = "ali1489",
|
|
.flags = 0,
|
|
.local = 0,
|
|
.init = ali1489_init,
|
|
.close = ali1489_close,
|
|
.reset = ali1489_reset,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|