126 lines
5.8 KiB
C
126 lines
5.8 KiB
C
#define SHIFT(size, size2, res_store, immediate) \
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if ((fetchdat & 0xc0) == 0xc0) \
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{ \
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reg = LOAD_REG_ ## size(fetchdat & 7); \
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if (immediate) count = (fetchdat >> 8) & 0x1f; \
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} \
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else \
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{ \
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target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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SAVE_EA(); \
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MEM_CHECK_WRITE_ ## size(target_seg); \
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reg = MEM_LOAD_ADDR_EA_ ## size ## _NO_ABRT(target_seg); \
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if (immediate) count = fastreadb(cs + op_pc + 1) & 0x1f; \
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} \
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, count); \
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\
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res_store((uintptr_t)&cpu_state.flags_op1, reg); \
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\
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switch (fetchdat & 0x38) \
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{ \
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case 0x20: case 0x30: /*SHL*/ \
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SHL_ ## size ## _IMM(reg, count); \
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \
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break; \
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\
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case 0x28: /*SHR*/ \
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SHR_ ## size ## _IMM(reg, count); \
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \
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break; \
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\
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case 0x38: /*SAR*/ \
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SAR_ ## size ## _IMM(reg, count); \
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \
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break; \
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} \
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\
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res_store((uintptr_t)&cpu_state.flags_res, reg); \
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if ((fetchdat & 0xc0) == 0xc0) \
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STORE_REG_ ## size ## _RELEASE(reg); \
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else \
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{ \
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LOAD_EA(); \
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MEM_STORE_ADDR_EA_ ## size ## _NO_ABRT(target_seg, reg); \
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}
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static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 1);
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return op_pc + 2;
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}
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static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 1);
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return op_pc + 2;
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}
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static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(L, 32, STORE_HOST_REG_ADDR, 1);
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return op_pc + 2;
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}
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static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count = 1;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 0);
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return op_pc + 1;
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}
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static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count = 1;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 0);
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return op_pc + 1;
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}
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static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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x86seg *target_seg = NULL;
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int count = 1;
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int reg;
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if ((fetchdat & 0x38) < 0x20)
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return 0;
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SHIFT(L, 32, STORE_HOST_REG_ADDR, 0);
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return op_pc + 1;
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}
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