263c48a49b
The datasheet only gave a small reference to it in passing. Port 92 is also implemented as it is also present on the 291.
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C291 chipset.
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* Authors: plant/nerd73
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*
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* Copyright 2020 plant/nerd73.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct
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{
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uint8_t index,
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regs[256];
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port_92_t *port_92;
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} opti291_t;
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static void opti291_recalc(opti291_t *dev)
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{
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uint32_t base;
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uint32_t i, shflags, write, writef = 0;
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writef = (dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
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if (!(dev->regs[0x23] & 0x40))
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | writef);
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else
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | writef);
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for (i = 0; i < 4; i++) {
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base = 0xe0000 + (i << 14);
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shflags = (dev->regs[0x24] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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write = (dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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shflags |= (dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : write;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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for (i = 0; i < 4; i++) {
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base = 0xd0000 + (i << 14);
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shflags = (dev->regs[0x25] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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write = (dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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shflags |= (dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : write;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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for (i = 0; i < 4; i++) {
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base = 0xc0000 + (i << 14);
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shflags = (dev->regs[0x26] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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write = (dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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shflags |= (dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : write;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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flushmmucache();
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}
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static void
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opti291_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti291_t *dev = (opti291_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x24:
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pclog("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val);
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dev->regs[dev->index] = val;
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switch(dev->index){
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case 0x21:
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cpu_update_waitstates();
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break;
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case 0x23:
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case 0x24:
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case 0x25:
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case 0x26:
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case 0x27:
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opti291_recalc(dev);
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break;
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}
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break;
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}
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}
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static uint8_t
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opti291_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti291_t *dev = (opti291_t *) priv;
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switch (addr) {
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case 0x24:
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// pclog("OPTi 291: read from dev->regs[%02x]\n", dev->index);
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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static void
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opti291_close(void *priv)
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{
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opti291_t *dev = (opti291_t *) priv;
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free(dev);
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}
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static void *
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opti291_init(const device_t *info)
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{
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opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t));
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memset(dev, 0, sizeof(opti291_t));
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io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
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io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
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dev->regs[0x23] = 0x40;
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dev->port_92 = device_add(&port_92_device);
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opti291_recalc(dev);
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return dev;
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}
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const device_t opti291_device = {
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"OPTi 82C291",
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0,
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0,
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opti291_init, opti291_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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