553 lines
16 KiB
C
553 lines
16 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the Winbond W83877 family of Super I/O Chips.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2016-2025 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/pci.h>
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#include <86box/mem.h>
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#include <86box/rom.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/machine.h>
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#include <86box/sio.h>
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#define FDDA_TYPE (dev->regs[0x07] & 3)
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#define FDDB_TYPE ((dev->regs[0x07] >> 2) & 3)
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#define FDDC_TYPE ((dev->regs[0x07] >> 4) & 3)
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#define FDDD_TYPE ((dev->regs[0x07] >> 6) & 3)
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#define FD_BOOT (dev->regs[0x08] & 3)
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#define SWWP ((dev->regs[0x08] >> 4) & 1)
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#define DISFDDWR ((dev->regs[0x08] >> 5) & 1)
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#define EN3MODE ((dev->regs[0x09] >> 5) & 1)
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#define DRV2EN_NEG (dev->regs[0x0b] & 1) /* 0 = drive 2 installed */
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#define INVERTZ ((dev->regs[0x0b] >> 1) & 1) /* 0 = invert DENSEL polarity */
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#define IDENT ((dev->regs[0x0b] >> 3) & 1)
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#define HEFERE ((dev->regs[0x0c] >> 5) & 1)
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#define HEFRAS (dev->regs[0x16] & 1)
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#define PRTIQS (dev->regs[0x27] & 0x0f)
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#define ECPIRQ ((dev->regs[0x27] >> 5) & 0x07)
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typedef struct w83877_t {
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uint8_t tries;
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uint8_t has_ide;
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uint8_t dma_map[4];
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uint8_t irq_map[10];
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uint8_t regs[256];
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uint16_t reg_init;
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int locked;
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int rw_locked;
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int cur_reg;
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int base_address;
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int key;
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int key_times;
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fdc_t *fdc;
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serial_t *uart[2];
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lpt_t *lpt;
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} w83877_t;
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static void w83877_write(uint16_t port, uint8_t val, void *priv);
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static uint8_t w83877_read(uint16_t port, void *priv);
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static void
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w83877_remap(w83877_t *dev)
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{
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uint8_t hefras = HEFRAS;
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io_removehandler(0x250, 0x0003,
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w83877_read, NULL, NULL, w83877_write, NULL, NULL, dev);
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io_removehandler(FDC_PRIMARY_ADDR, 0x0002,
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w83877_read, NULL, NULL, w83877_write, NULL, NULL, dev);
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dev->base_address = (hefras ? FDC_PRIMARY_ADDR : 0x250);
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io_sethandler(dev->base_address, hefras ? 0x0002 : 0x0003,
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w83877_read, NULL, NULL, w83877_write, NULL, NULL, dev);
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dev->key_times = hefras + 1;
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dev->key = (hefras ? 0x86 : 0x88) | HEFERE;
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}
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static uint8_t
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get_lpt_length(w83877_t *dev)
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{
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uint8_t length = 4;
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if (dev->regs[0x09] & 0x80) {
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if (dev->regs[0x00] & 0x04)
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length = 8; /* EPP mode. */
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if (dev->regs[0x00] & 0x08)
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length |= 0x80; /* ECP mode. */
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}
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return length;
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}
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static uint16_t
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make_port(w83877_t *dev, uint8_t reg)
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{
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uint16_t p = 0;
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uint8_t l;
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switch (reg) {
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case 0x20:
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p = ((uint16_t) (dev->regs[reg] & 0xfc)) << 2;
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p &= 0x0ff0;
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if ((p < 0x0100) || (p > 0x03f0))
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p = 0x03f0;
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break;
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case 0x23:
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l = get_lpt_length(dev);
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p = ((uint16_t) (dev->regs[reg] & 0xff)) << 2;
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/* 8 ports in EPP mode, 4 in non-EPP mode. */
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if ((l & 0x0f) == 8)
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p &= 0x03f8;
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else
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p &= 0x03fc;
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if ((p < 0x0100) || (p > 0x03ff))
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p = LPT1_ADDR;
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break;
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case 0x24:
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p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
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p &= 0x0ff8;
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if ((p < 0x0100) || (p > 0x03f8))
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p = COM1_ADDR;
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break;
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case 0x25:
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p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
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p &= 0x0ff8;
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if ((p < 0x0100) || (p > 0x03f8))
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p = COM2_ADDR;
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break;
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default:
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break;
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}
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return p;
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}
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static void
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w83877_ide_handler(w83877_t *dev)
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{
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uint16_t ide_port = 0x0000;
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if (dev->has_ide > 0) {
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int ide_id = dev->has_ide - 1;
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ide_handlers(ide_id, 0);
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ide_port = (dev->regs[0x21] << 2) & 0xfff0;
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ide_set_base_addr(ide_id, 0, ide_port);
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ide_port = ((dev->regs[0x22] << 2) & 0xfff0) | 0x0006;
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ide_set_base_addr(ide_id, 1, ide_port);
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if (!(dev->regs[0x06] & 0x04))
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ide_handlers(ide_id, 1);
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}
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}
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static void
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w83877_fdc_handler(w83877_t *dev)
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{
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fdc_remove(dev->fdc);
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if (!(dev->regs[0x06] & 0x08) && (dev->regs[0x20] & 0xc0))
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fdc_set_base(dev->fdc, make_port(dev, 0x20));
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fdc_set_irq(dev->fdc, dev->irq_map[dev->regs[0x29] >> 4]);
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fdc_set_dma_ch(dev->fdc, dev->dma_map[(dev->regs[0x26] >> 4) & 0x03]);
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fdc_set_power_down(dev->fdc, !!(dev->regs[0x06] & 0x08));
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}
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static void
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w83877_lpt_handler(w83877_t *dev)
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{
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const uint8_t lpt_irq = dev->irq_map[PRTIQS];
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lpt_port_remove(dev->lpt);
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lpt_set_ext(dev->lpt, 1);
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lpt_set_epp(dev->lpt, (dev->regs[0x09] & 0x80) && (dev->regs[0x00] & 0x04));
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lpt_set_ecp(dev->lpt, (dev->regs[0x09] & 0x80) && (dev->regs[0x00] & 0x08));
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lpt_set_fifo_threshold(dev->lpt, dev->regs[0x05] & 0x0f);
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if (!(dev->regs[0x04] & 0x80) && (dev->regs[0x23] & 0xc0))
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lpt_port_setup(dev->lpt, make_port(dev, 0x23));
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lpt_port_irq(dev->lpt, lpt_irq);
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lpt_port_dma(dev->lpt, dev->dma_map[dev->regs[0x26] & 0x03]);
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}
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static void
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w83877_serial_handler(w83877_t *dev, int uart)
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{
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int reg_mask = uart ? 0x10 : 0x20;
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int reg_id = uart ? 0x25 : 0x24;
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int irq_mask = uart ? 0x0f : 0xf0;
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int irq_shift = uart ? 0 : 4;
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double clock_src = 24000000.0 / 13.0;
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serial_remove(dev->uart[uart]);
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if (!(dev->regs[4] & reg_mask) && (dev->regs[reg_id] & 0xc0))
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serial_setup(dev->uart[uart], make_port(dev, reg_id), dev->irq_map[(dev->regs[0x28] & irq_mask) >> irq_shift]);
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if (dev->regs[0x19] & (0x02 >> uart)) {
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clock_src = 14769000.0;
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} else if (dev->regs[0x03] & (0x02 >> uart)) {
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clock_src = 24000000.0 / 12.0;
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} else {
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clock_src = 24000000.0 / 13.0;
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}
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serial_set_clock_src(dev->uart[uart], clock_src);
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}
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static void
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w83877_write(uint16_t port, uint8_t val, void *priv)
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{
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w83877_t *dev = (w83877_t *) priv;
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uint8_t valxor = 0;
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if (port == 0x0250) {
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if (val == dev->key)
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dev->locked = 1;
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else
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dev->locked = 0;
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return;
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} else if (port == 0x0251) {
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dev->cur_reg = val;
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return;
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} else if (port == FDC_PRIMARY_ADDR) {
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if ((val == dev->key) && !dev->locked) {
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if (dev->key_times == 2) {
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if (dev->tries) {
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dev->locked = 1;
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dev->tries = 0;
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} else
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dev->tries++;
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} else {
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dev->locked = 1;
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dev->tries = 0;
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}
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} else {
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if (dev->locked) {
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dev->cur_reg = val;
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if (val == 0xaa)
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dev->locked = 0;
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} else {
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if (dev->tries)
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dev->tries = 0;
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}
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}
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return;
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} else if ((port == 0x0252) || (port == 0x03f1)) {
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if (dev->locked) {
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if (dev->rw_locked)
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return;
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valxor = val ^ dev->regs[dev->cur_reg];
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dev->regs[dev->cur_reg] = val;
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} else
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return;
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}
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switch (dev->cur_reg) {
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case 0x00:
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if (valxor & 0x0c)
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w83877_lpt_handler(dev);
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break;
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case 0x01:
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if (valxor & 0x80)
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fdc_set_swap(dev->fdc, (dev->regs[0x01] & 0x80) ? 1 : 0);
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break;
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case 0x03:
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if (valxor & 0x02)
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w83877_serial_handler(dev, 0);
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if (valxor & 0x01)
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w83877_serial_handler(dev, 1);
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break;
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case 0x04:
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if (valxor & 0x10)
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w83877_serial_handler(dev, 1);
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if (valxor & 0x20)
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w83877_serial_handler(dev, 0);
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if (valxor & 0x80)
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w83877_lpt_handler(dev);
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break;
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case 0x05:
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if (valxor & 0x0f)
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w83877_lpt_handler(dev);
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break;
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case 0x06:
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if (valxor & 0x08)
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w83877_fdc_handler(dev);
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if (valxor & 0x04)
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w83877_ide_handler(dev);
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break;
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case 0x07:
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if (valxor & 0x03)
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fdc_update_rwc(dev->fdc, 0, FDDA_TYPE);
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if (valxor & 0x0c)
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fdc_update_rwc(dev->fdc, 1, FDDB_TYPE);
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if (valxor & 0x30)
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fdc_update_rwc(dev->fdc, 2, FDDC_TYPE);
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if (valxor & 0xc0)
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fdc_update_rwc(dev->fdc, 3, FDDD_TYPE);
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break;
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case 0x08:
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if (valxor & 0x03)
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fdc_update_boot_drive(dev->fdc, FD_BOOT);
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if (valxor & 0x10)
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fdc_set_swwp(dev->fdc, SWWP ? 1 : 0);
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if (valxor & 0x20)
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fdc_set_diswr(dev->fdc, DISFDDWR ? 1 : 0);
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break;
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case 0x09:
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if (valxor & 0x20)
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fdc_update_enh_mode(dev->fdc, EN3MODE ? 1 : 0);
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if (valxor & 0x40)
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dev->rw_locked = (val & 0x40) ? 1 : 0;
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if (valxor & 0x80)
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w83877_lpt_handler(dev);
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break;
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case 0x0b:
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if (valxor & 0x0c) {
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fdc_clear_flags(dev->fdc, FDC_FLAG_PS2 | FDC_FLAG_PS2_MCA);
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switch (val & 0x0c) {
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case 0x00:
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fdc_set_flags(dev->fdc, FDC_FLAG_PS2);
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break;
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case 0x04:
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fdc_set_flags(dev->fdc, FDC_FLAG_PS2_MCA);
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break;
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}
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}
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if (valxor & 0x02)
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fdc_update_densel_polarity(dev->fdc, INVERTZ ? 1 : 0);
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if (valxor & 0x01)
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fdc_update_drv2en(dev->fdc, DRV2EN_NEG ? 0 : 1);
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break;
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case 0x0c:
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if (valxor & 0x20)
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w83877_remap(dev);
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break;
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case 0x16:
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if (valxor & 0x02) {
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dev->regs[0x1e] = (val & 0x02) ? 0x81 : 0x00;
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dev->regs[0x20] = (val & 0x02) ? 0xfc : 0x00;
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dev->regs[0x21] = (val & 0x02) ? 0x7c : 0x00;
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dev->regs[0x22] = (val & 0x02) ? 0xfd : 0x00;
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dev->regs[0x23] = (val & 0x02) ? 0xde : 0x00;
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dev->regs[0x24] = (val & 0x02) ? 0xfe : 0x00;
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dev->regs[0x25] = (val & 0x02) ? 0xbe : 0x00;
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dev->regs[0x26] = (val & 0x02) ? 0x23 : 0x00;
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dev->regs[0x27] = (val & 0x02) ? 0x65 : 0x00;
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dev->regs[0x28] = (val & 0x02) ? 0x43 : 0x00;
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dev->regs[0x29] = (val & 0x02) ? 0x62 : 0x00;
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w83877_fdc_handler(dev);
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w83877_lpt_handler(dev);
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w83877_serial_handler(dev, 0);
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w83877_serial_handler(dev, 1);
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}
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if (valxor & 0x01)
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w83877_remap(dev);
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break;
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case 0x19:
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if (valxor & 0x02)
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w83877_serial_handler(dev, 0);
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if (valxor & 0x01)
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w83877_serial_handler(dev, 1);
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break;
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case 0x20:
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if (valxor)
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w83877_fdc_handler(dev);
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break;
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case 0x21: case 0x22:
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if (valxor)
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w83877_ide_handler(dev);
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break;
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case 0x23:
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if (valxor)
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w83877_lpt_handler(dev);
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break;
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case 0x24:
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if (valxor & 0xfe)
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w83877_serial_handler(dev, 0);
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break;
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case 0x25:
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if (valxor & 0xfe)
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w83877_serial_handler(dev, 1);
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break;
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case 0x26:
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if (valxor & 0x0f)
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w83877_lpt_handler(dev);
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break;
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case 0x27:
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if (valxor & 0xef)
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w83877_lpt_handler(dev);
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break;
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case 0x28:
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if (valxor & 0x0f) {
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if ((dev->regs[0x28] & 0x0f) == 0)
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dev->regs[0x28] |= 0x03;
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w83877_serial_handler(dev, 1);
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}
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if (valxor & 0xf0) {
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if ((dev->regs[0x28] & 0xf0) == 0)
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dev->regs[0x28] |= 0x40;
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w83877_serial_handler(dev, 0);
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}
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break;
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case 0x29:
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if (valxor & 0xf0)
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w83877_fdc_handler(dev);
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break;
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default:
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break;
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}
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}
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static uint8_t
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w83877_read(uint16_t port, void *priv)
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{
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w83877_t *dev = (w83877_t *) priv;
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uint8_t ret = 0xff;
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if (dev->locked) {
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if ((port == FDC_PRIMARY_ADDR) || (port == 0x251))
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ret = dev->cur_reg;
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else if ((port == 0x3f1) || (port == 0x252)) {
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if (dev->cur_reg == 7)
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ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
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else if ((dev->cur_reg >= 0x18) || !dev->rw_locked)
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ret = dev->regs[dev->cur_reg];
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}
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}
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return ret;
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}
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static void
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w83877_reset(w83877_t *dev)
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{
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fdc_reset(dev->fdc);
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memset(dev->regs, 0, 0x2A);
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dev->regs[0x03] = 0x30;
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dev->regs[0x07] = 0xF5;
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dev->regs[0x09] = (dev->reg_init >> 8) & 0xff;
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dev->regs[0x0a] = 0x1F;
|
|
dev->regs[0x0c] = 0x28;
|
|
dev->regs[0x0d] = 0xA3;
|
|
dev->regs[0x16] = dev->reg_init & 0xff;
|
|
|
|
w83877_fdc_handler(dev);
|
|
fdc_clear_flags(dev->fdc, FDC_FLAG_PS2 | FDC_FLAG_PS2_MCA);
|
|
|
|
w83877_lpt_handler(dev);
|
|
|
|
w83877_serial_handler(dev, 0);
|
|
w83877_serial_handler(dev, 1);
|
|
|
|
if (dev->has_ide)
|
|
w83877_ide_handler(dev);
|
|
|
|
dev->base_address = FDC_PRIMARY_ADDR;
|
|
dev->key = 0x89;
|
|
dev->key_times = 1;
|
|
|
|
w83877_remap(dev);
|
|
|
|
dev->locked = 0;
|
|
dev->rw_locked = 0;
|
|
}
|
|
|
|
static void
|
|
w83877_close(void *priv)
|
|
{
|
|
w83877_t *dev = (w83877_t *) priv;
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
w83877_init(const device_t *info)
|
|
{
|
|
w83877_t *dev = (w83877_t *) calloc(1, sizeof(w83877_t));
|
|
|
|
dev->fdc = device_add(&fdc_at_winbond_device);
|
|
|
|
dev->uart[0] = device_add_inst(&ns16550_device, 1);
|
|
dev->uart[1] = device_add_inst(&ns16550_device, 2);
|
|
|
|
dev->lpt = device_add_inst(&lpt_port_device, 1);
|
|
|
|
dev->reg_init = info->local;
|
|
|
|
dev->has_ide = (info->local >> 16) & 0xff;
|
|
|
|
if (!strcmp(machine_get_internal_name(), "ficpa2012")) {
|
|
dev->dma_map[0] = 4;
|
|
dev->dma_map[1] = 3;
|
|
dev->dma_map[2] = 1;
|
|
dev->dma_map[3] = 2;
|
|
} else {
|
|
dev->dma_map[0] = 4;
|
|
for (int i = 1; i < 4; i++)
|
|
dev->dma_map[i] = i;
|
|
}
|
|
|
|
memset(dev->irq_map, 0xff, 16);
|
|
dev->irq_map[0] = 0xff;
|
|
for (int i = 1; i < 7; i++)
|
|
dev->irq_map[i] = i;
|
|
dev->irq_map[1] = 5;
|
|
dev->irq_map[5] = 7;
|
|
dev->irq_map[7] = 9; /* Guesswork, I can't find a single BIOS that lets me assign IRQ_G to something. */
|
|
dev->irq_map[8] = 10;
|
|
|
|
w83877_reset(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t w83877_device = {
|
|
.name = "Winbond W83877F Super I/O",
|
|
.internal_name = "w83877",
|
|
.flags = 0,
|
|
.local = 0,
|
|
.init = w83877_init,
|
|
.close = w83877_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|