51bbebbfa3
- Disabled the 'is486' flag and moved them to 386 timings - Disabled cache on startup, enable-able later - RapidCAD fixes (permanently disable L1, correct EDX reset)
457 lines
24 KiB
C
457 lines
24 KiB
C
static int opARPL_a16(uint32_t fetchdat)
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{
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uint16_t temp_seg;
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NOTRM
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fetch_ea_16(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp_seg = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
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{
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temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
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seteaw(temp_seg); if (cpu_state.abrt) return 1;
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cpu_state.flags |= Z_FLAG;
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}
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else
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cpu_state.flags &= ~Z_FLAG;
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CLOCK_CYCLES(is486 ? 9 : 20);
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PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 0);
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return 0;
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}
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static int opARPL_a32(uint32_t fetchdat)
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{
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uint16_t temp_seg;
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NOTRM
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fetch_ea_32(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp_seg = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
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{
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temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
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seteaw(temp_seg); if (cpu_state.abrt) return 1;
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cpu_state.flags |= Z_FLAG;
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}
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else
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cpu_state.flags &= ~Z_FLAG;
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CLOCK_CYCLES(is486 ? 9 : 20);
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PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 1);
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return 0;
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}
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#define opLAR(name, fetch_ea, is32, ea32) \
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static int opLAR_ ## name(uint32_t fetchdat) \
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{ \
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int valid; \
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uint16_t sel, desc = 0; \
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\
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NOTRM \
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fetch_ea(fetchdat); \
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if (cpu_mod != 3) \
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SEG_CHECK_READ(cpu_state.ea_seg); \
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\
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sel = geteaw(); if (cpu_state.abrt) return 1; \
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\
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flags_rebuild(); \
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if (!(sel & 0xfffc)) { cpu_state.flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
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if (valid) \
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{ \
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cpl_override = 1; \
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
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cpl_override = 0; if (cpu_state.abrt) return 1; \
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} \
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cpu_state.flags &= ~Z_FLAG; \
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if ((desc & 0x1f00) == 0x000) valid = 0; \
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if ((desc & 0x1f00) == 0x800) valid = 0; \
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if ((desc & 0x1f00) == 0xa00) valid = 0; \
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if ((desc & 0x1f00) == 0xd00) valid = 0; \
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if ((desc & 0x1c00) < 0x1c00) /*Exclude conforming code segments*/ \
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{ \
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int dpl = (desc >> 13) & 3; \
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if (dpl < CPL || dpl < (sel & 3)) valid = 0; \
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} \
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if (valid) \
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{ \
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cpu_state.flags |= Z_FLAG; \
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cpl_override = 1; \
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if (is32) \
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cpu_state.regs[cpu_reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
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else \
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cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
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cpl_override = 0; \
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} \
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CLOCK_CYCLES(11); \
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PREFETCH_RUN(11, 2, rmdat, 2,0,0,0, ea32); \
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return cpu_state.abrt; \
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}
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opLAR(w_a16, fetch_ea_16, 0, 0)
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opLAR(w_a32, fetch_ea_32, 0, 1)
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opLAR(l_a16, fetch_ea_16, 1, 0)
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opLAR(l_a32, fetch_ea_32, 1, 1)
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#define opLSL(name, fetch_ea, is32, ea32) \
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static int opLSL_ ## name(uint32_t fetchdat) \
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{ \
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int valid; \
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uint16_t sel, desc = 0; \
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\
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NOTRM \
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fetch_ea(fetchdat); \
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if (cpu_mod != 3) \
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SEG_CHECK_READ(cpu_state.ea_seg); \
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\
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sel = geteaw(); if (cpu_state.abrt) return 1; \
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flags_rebuild(); \
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cpu_state.flags &= ~Z_FLAG; \
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if (!(sel & 0xfffc)) return 0; /*Null selector*/ \
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
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if (valid) \
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{ \
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cpl_override = 1; \
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
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cpl_override = 0; if (cpu_state.abrt) return 1; \
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} \
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if ((desc & 0x1400) == 0x400) valid = 0; /*Interrupt or trap or call gate*/ \
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if ((desc & 0x1f00) == 0x000) valid = 0; /*Invalid*/ \
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if ((desc & 0x1f00) == 0xa00) valid = 0; /*Invalid*/ \
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if ((desc & 0x1c00) != 0x1c00) /*Exclude conforming code segments*/ \
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{ \
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int rpl = (desc >> 13) & 3; \
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if (rpl < CPL || rpl < (sel & 3)) valid = 0; \
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} \
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if (valid) \
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{ \
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cpu_state.flags |= Z_FLAG; \
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cpl_override = 1; \
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if (is32) \
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{ \
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cpu_state.regs[cpu_reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
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cpu_state.regs[cpu_reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
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if (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0x80) \
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{ \
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cpu_state.regs[cpu_reg].l <<= 12; \
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cpu_state.regs[cpu_reg].l |= 0xFFF; \
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} \
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} \
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else \
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cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
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cpl_override = 0; \
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} \
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CLOCK_CYCLES(10); \
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PREFETCH_RUN(10, 2, rmdat, 4,0,0,0, ea32); \
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return cpu_state.abrt; \
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}
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opLSL(w_a16, fetch_ea_16, 0, 0)
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opLSL(w_a32, fetch_ea_32, 0, 1)
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opLSL(l_a16, fetch_ea_16, 1, 0)
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opLSL(l_a32, fetch_ea_32, 1, 1)
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static int op0F00_common(uint32_t fetchdat, int ea32)
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{
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int dpl, valid, granularity;
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uint32_t addr, base, limit;
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uint16_t desc, sel;
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uint8_t access;
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switch (rmdat & 0x38)
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{
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case 0x00: /*SLDT*/
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(ldt.seg);
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
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break;
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case 0x08: /*STR*/
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(tr.seg);
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
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break;
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case 0x10: /*LLDT*/
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if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
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{
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x86gpf(NULL,0);
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return 1;
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}
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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sel = geteaw(); if (cpu_state.abrt) return 1;
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addr = (sel & ~7) + gdt.base;
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limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
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base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
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access = readmemb(0, addr + 5);
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granularity = readmemb(0, addr + 6) & 0x80;
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if (cpu_state.abrt) return 1;
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ldt.limit = limit;
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ldt.access = access;
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if (granularity)
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{
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ldt.limit <<= 12;
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ldt.limit |= 0xfff;
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}
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ldt.base = base;
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ldt.seg = sel;
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
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break;
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case 0x18: /*LTR*/
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if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
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{
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x86gpf(NULL,0);
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break;
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}
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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sel = geteaw(); if (cpu_state.abrt) return 1;
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addr = (sel & ~7) + gdt.base;
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limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
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base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
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access = readmemb(0, addr + 5);
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granularity = readmemb(0, addr + 6) & 0x80;
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if (cpu_state.abrt) return 1;
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access |= 2;
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writememb(0, addr + 5, access);
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if (cpu_state.abrt) return 1;
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tr.seg = sel;
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tr.limit = limit;
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tr.access = access;
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if (granularity)
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{
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tr.limit <<= 12;
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tr.limit |= 0xFFF;
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}
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tr.base = base;
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
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break;
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case 0x20: /*VERR*/
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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sel = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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cpu_state.flags &= ~Z_FLAG;
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if (!(sel & 0xfffc)) return 0; /*Null selector*/
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cpl_override = 1;
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
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cpl_override = 0; if (cpu_state.abrt) return 1;
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if (!(desc & 0x1000)) valid = 0;
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if ((desc & 0xC00) != 0xC00) /*Exclude conforming code segments*/
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{
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dpl = (desc >> 13) & 3; /*Check permissions*/
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if (dpl < CPL || dpl < (sel & 3)) valid = 0;
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}
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if ((desc & 0x0800) && !(desc & 0x0200)) valid = 0; /*Non-readable code*/
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if (valid) cpu_state.flags |= Z_FLAG;
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
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break;
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case 0x28: /*VERW*/
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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sel = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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cpu_state.flags &= ~Z_FLAG;
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if (!(sel & 0xfffc)) return 0; /*Null selector*/
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cpl_override = 1;
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
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cpl_override = 0; if (cpu_state.abrt) return 1;
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if (!(desc & 0x1000)) valid = 0;
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dpl = (desc >> 13) & 3; /*Check permissions*/
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if (dpl < CPL || dpl < (sel & 3)) valid = 0;
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if (desc & 0x0800) valid = 0; /*Code*/
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if (!(desc & 0x0200)) valid = 0; /*Read-only data*/
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if (valid) cpu_state.flags |= Z_FLAG;
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
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break;
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default:
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cpu_state.pc -= 3;
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x86illegal();
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break;
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}
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return cpu_state.abrt;
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}
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static int op0F00_a16(uint32_t fetchdat)
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{
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NOTRM
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fetch_ea_16(fetchdat);
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return op0F00_common(fetchdat, 0);
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}
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static int op0F00_a32(uint32_t fetchdat)
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{
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NOTRM
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fetch_ea_32(fetchdat);
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return op0F00_common(fetchdat, 1);
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}
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static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
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{
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uint32_t base;
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uint16_t limit, tempw;
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switch (rmdat & 0x38)
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{
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case 0x00: /*SGDT*/
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(gdt.limit);
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base = gdt.base; //is32 ? gdt.base : (gdt.base & 0xffffff);
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if (is286)
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base |= 0xff000000;
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writememl(easeg, cpu_state.eaaddr + 2, base);
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
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break;
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case 0x08: /*SIDT*/
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(idt.limit);
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base = idt.base;
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if (is286)
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base |= 0xff000000;
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writememl(easeg, cpu_state.eaaddr + 2, base);
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
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break;
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case 0x10: /*LGDT*/
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if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
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{
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x86gpf(NULL,0);
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break;
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}
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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limit = geteaw();
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
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gdt.limit = limit;
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gdt.base = base;
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if (!is32) gdt.base &= 0xffffff;
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CLOCK_CYCLES(11);
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PREFETCH_RUN(11, 2, rmdat, 1,1,0,0, ea32);
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break;
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case 0x18: /*LIDT*/
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if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
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{
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x86gpf(NULL,0);
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break;
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}
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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limit = geteaw();
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
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idt.limit = limit;
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idt.base = base;
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if (!is32) idt.base &= 0xffffff;
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CLOCK_CYCLES(11);
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PREFETCH_RUN(11, 2, rmdat, 1,1,0,0, ea32);
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break;
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case 0x20: /*SMSW*/
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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if (is486 || isibm486) seteaw(msw);
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else if (is386) seteaw(msw | 0xFF00);
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else seteaw(msw | 0xFFF0);
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
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break;
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case 0x30: /*LMSW*/
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if ((CPL || cpu_state.eflags&VM_FLAG) && (msw&1))
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{
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x86gpf(NULL, 0);
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break;
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}
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if (cpu_mod != 3)
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SEG_CHECK_READ(cpu_state.ea_seg);
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tempw = geteaw(); if (cpu_state.abrt) return 1;
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if (msw & 1) tempw |= 1;
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if (is386)
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{
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tempw &= ~0x10;
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tempw |= (msw & 0x10);
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}
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else tempw &= 0xF;
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msw = tempw;
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if (msw & 1)
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cpu_cur_status |= CPU_STATUS_PMODE;
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else
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cpu_cur_status &= ~CPU_STATUS_PMODE;
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PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
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break;
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case 0x38: /*INVLPG*/
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if (is486 || isibm486)
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{
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if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
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{
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x86gpf(NULL, 0);
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break;
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}
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SEG_CHECK_READ(cpu_state.ea_seg);
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mmu_invalidate(ds + cpu_state.eaaddr);
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CLOCK_CYCLES(12);
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PREFETCH_RUN(12, 2, rmdat, 0,0,0,0, ea32);
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break;
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}
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default:
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cpu_state.pc -= 3;
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x86illegal();
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break;
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}
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return cpu_state.abrt;
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}
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static int op0F01_w_a16(uint32_t fetchdat)
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{
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fetch_ea_16(fetchdat);
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return op0F01_common(fetchdat, 0, 0, 0);
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}
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static int op0F01_w_a32(uint32_t fetchdat)
|
|
{
|
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fetch_ea_32(fetchdat);
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|
|
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return op0F01_common(fetchdat, 0, 0, 1);
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}
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static int op0F01_l_a16(uint32_t fetchdat)
|
|
{
|
|
fetch_ea_16(fetchdat);
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|
|
|
return op0F01_common(fetchdat, 1, 0, 0);
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|
}
|
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static int op0F01_l_a32(uint32_t fetchdat)
|
|
{
|
|
fetch_ea_32(fetchdat);
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|
|
|
return op0F01_common(fetchdat, 1, 0, 1);
|
|
}
|
|
|
|
static int op0F01_286(uint32_t fetchdat)
|
|
{
|
|
fetch_ea_16(fetchdat);
|
|
|
|
return op0F01_common(fetchdat, 0, 1, 0);
|
|
}
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