460 lines
13 KiB
C
460 lines
13 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SiS 5571 Host to PCI bridge.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2024 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/dma.h>
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#include <86box/mem.h>
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#include <86box/nvr.h>
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#include <86box/hdd.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/pit.h>
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#include <86box/pit_fast.h>
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#include <86box/plat.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/smram.h>
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#include <86box/spd.h>
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#include <86box/apm.h>
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#include <86box/ddma.h>
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#include <86box/acpi.h>
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#include <86box/smbus.h>
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#include <86box/spd.h>
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#include <86box/sis_55xx.h>
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#include <86box/chipset.h>
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#include <86box/usb.h>
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#include <86box/agpgart.h>
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#ifdef ENABLE_SIS_5571_HOST_TO_PCI_LOG
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int sis_5571_host_to_pci_do_log = ENABLE_SIS_5571_HOST_TO_PCI_LOG;
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static void
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sis_5571_host_to_pci_log(const char *fmt, ...)
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{
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va_list ap;
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if (sis_5571_host_to_pci_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define sis_5571_host_to_pci_log(fmt, ...)
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#endif
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typedef struct sis_5571_host_to_pci_t {
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uint8_t pci_conf[256];
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uint8_t states[7];
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sis_55xx_common_t *sis;
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smram_t *smram;
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} sis_5571_host_to_pci_t;
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static void
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sis_5571_shadow_recalc(sis_5571_host_to_pci_t *dev)
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{
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int state;
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uint32_t base;
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for (uint8_t i = 0x70; i <= 0x76; i++) {
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if (i == 0x76) {
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if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
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state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state_both(0xf0000, 0x10000, state);
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sis_5571_host_to_pci_log("000F0000-000FFFFF\n");
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}
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} else {
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base = ((i & 0x07) << 15) + 0xc0000;
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if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
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state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state_both(base, 0x4000, state);
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sis_5571_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
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}
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if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0x0a) {
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state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state_both(base + 0x4000, 0x4000, state);
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sis_5571_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
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}
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}
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dev->states[i & 0x0f] = dev->pci_conf[i];
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}
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flushmmucache_nopc();
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}
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static void
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sis_5571_smram_recalc(sis_5571_host_to_pci_t *dev)
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{
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smram_disable_all();
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switch (dev->pci_conf[0xa3] >> 6) {
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case 0:
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smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
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break;
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case 1:
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smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
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break;
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case 2:
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smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
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break;
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case 3:
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smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0xa3] & 0x10, 1);
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break;
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default:
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break;
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}
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flushmmucache();
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}
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void
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sis_5571_host_to_pci_write(int addr, uint8_t val, void *priv)
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{
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sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
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sis_5571_host_to_pci_log("SiS 5571 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
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switch (addr) {
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default:
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break;
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case 0x04: /* Command - low byte */
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case 0x05: /* Command - high byte */
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dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfd) | (val & 0x02);
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break;
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case 0x07: /* Status - High Byte */
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dev->pci_conf[addr] &= ~(val & 0xb8);
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break;
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case 0x0d: /* Master latency timer */
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dev->pci_conf[addr] = val;
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break;
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case 0x50: /* Host Interface and DRAM arbiter */
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dev->pci_conf[addr] = val & 0xec;
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break;
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case 0x51: /* CACHE */
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dev->pci_conf[addr] = val;
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cpu_cache_ext_enabled = !!(val & 0x40);
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cpu_update_waitstates();
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break;
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case 0x52:
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dev->pci_conf[addr] = val & 0xd0;
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break;
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case 0x53: /* DRAM */
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dev->pci_conf[addr] = val & 0xfe;
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break;
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case 0x54: /* FP/EDO */
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dev->pci_conf[addr] = val;
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break;
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case 0x55:
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dev->pci_conf[addr] = val & 0xe0;
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break;
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case 0x56: /* MDLE delay */
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dev->pci_conf[addr] = val & 0x07;
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break;
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case 0x57: /* SDRAM */
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x59: /* Buffer strength and current rating */
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dev->pci_conf[addr] = val;
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break;
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case 0x5a:
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dev->pci_conf[addr] = val & 0x03;
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break;
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/* Undocumented - DRAM bank registers, the exact layout is currently unknown. */
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case 0x60 ... 0x6b:
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dev->pci_conf[addr] = val;
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break;
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case 0x70 ... 0x75:
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dev->pci_conf[addr] = val & 0xee;
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sis_5571_shadow_recalc(dev);
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break;
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case 0x76:
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dev->pci_conf[addr] = val & 0xe8;
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sis_5571_shadow_recalc(dev);
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break;
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case 0x77: /* Characteristics of non-cacheable area */
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dev->pci_conf[addr] = val & 0x0f;
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break;
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case 0x78: /* Allocation of Non-Cacheable area #1 */
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case 0x79: /* NCA1REG2 */
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case 0x7a: /* Allocation of Non-Cacheable area #2 */
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case 0x7b: /* NCA2REG2 */
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dev->pci_conf[addr] = val;
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break;
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case 0x80: /* PCI master characteristics */
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dev->pci_conf[addr] = val & 0xfe;
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break;
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case 0x81:
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dev->pci_conf[addr] = val & 0xcc;
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break;
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case 0x82:
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dev->pci_conf[addr] = val;
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break;
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case 0x83: /* CPU to PCI characteristics */
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dev->pci_conf[addr] = val;
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/* TODO: Implement Fast A20 and Fast reset stuff on the KBC already! */
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break;
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case 0x84 ... 0x86:
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dev->pci_conf[addr] = val;
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break;
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case 0x87: /* Miscellanea */
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x90: /* PMU control register */
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case 0x91: /* Address trap for green function */
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case 0x92:
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dev->pci_conf[addr] = val;
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break;
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case 0x93: /* STPCLK# and APM SMI control */
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dev->pci_conf[addr] = val;
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if ((dev->pci_conf[0x9b] & 0x01) && (val & 0x02)) {
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smi_raise();
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dev->pci_conf[0x9d] |= 0x01;
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}
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break;
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case 0x94: /* 6x86 and Green function control */
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x95: /* Test mode control */
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case 0x96: /* Time slot and Programmable 10-bit I/O port definition */
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dev->pci_conf[addr] = val & 0xfb;
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break;
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case 0x97: /* programmable 10-bit I/O port address */
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case 0x98: /* Programmable 16-bit I/O port */
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case 0x99 ... 0x9c:
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dev->pci_conf[addr] = val;
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break;
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case 0x9d:
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dev->pci_conf[addr] &= val;
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break;
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case 0x9e: /* STPCLK# Assertion Timer */
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case 0x9f: /* STPCLK# De-assertion Timer */
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case 0xa0 ... 0xa2:
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dev->pci_conf[addr] = val;
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break;
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case 0xa3: /* SMRAM access control and Power supply control */
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dev->pci_conf[addr] = val & 0xd0;
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sis_5571_smram_recalc(dev);
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break;
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}
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}
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uint8_t
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sis_5571_host_to_pci_read(int addr, void *priv)
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{
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const sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->pci_conf[addr];
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sis_5571_host_to_pci_log("SiS 5571 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
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return ret;
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}
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static void
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sis_5571_host_to_pci_reset(void *priv)
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{
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sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
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dev->pci_conf[0x00] = 0x39;
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x71;
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dev->pci_conf[0x03] = 0x55;
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dev->pci_conf[0x04] = 0x05;
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dev->pci_conf[0x05] = 0x00;
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dev->pci_conf[0x06] = 0x00;
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dev->pci_conf[0x07] = 0x02;
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dev->pci_conf[0x08] = 0x00;
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dev->pci_conf[0x09] = 0x00;
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dev->pci_conf[0x0a] = 0x00;
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dev->pci_conf[0x0b] = 0x06;
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dev->pci_conf[0x0c] = 0x00;
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dev->pci_conf[0x0d] = 0x00;
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dev->pci_conf[0x0e] = 0x00;
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dev->pci_conf[0x0f] = 0x00;
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dev->pci_conf[0x50] = 0x00;
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dev->pci_conf[0x51] = 0x00;
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dev->pci_conf[0x52] = 0x00;
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dev->pci_conf[0x53] = 0x00;
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dev->pci_conf[0x54] = 0x54;
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dev->pci_conf[0x55] = 0x54;
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dev->pci_conf[0x56] = 0x03;
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dev->pci_conf[0x57] = 0x00;
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dev->pci_conf[0x58] = 0x00;
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dev->pci_conf[0x59] = 0x00;
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dev->pci_conf[0x5a] = 0x00;
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/* Undocumented DRAM bank registers. */
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dev->pci_conf[0x60] = dev->pci_conf[0x62] = 0x04;
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dev->pci_conf[0x64] = dev->pci_conf[0x66] = 0x04;
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dev->pci_conf[0x68] = dev->pci_conf[0x6a] = 0x04;
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dev->pci_conf[0x61] = dev->pci_conf[0x65] = 0x00;
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dev->pci_conf[0x63] = dev->pci_conf[0x67] = 0x80;
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dev->pci_conf[0x69] = 0x00;
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dev->pci_conf[0x6b] = 0x80;
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dev->pci_conf[0x70] = 0x00;
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dev->pci_conf[0x71] = 0x00;
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dev->pci_conf[0x72] = 0x00;
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dev->pci_conf[0x73] = 0x00;
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dev->pci_conf[0x74] = 0x00;
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dev->pci_conf[0x75] = 0x00;
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dev->pci_conf[0x76] = 0x00;
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dev->pci_conf[0x77] = 0x00;
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dev->pci_conf[0x78] = 0x00;
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dev->pci_conf[0x79] = 0x00;
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dev->pci_conf[0x7a] = 0x00;
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dev->pci_conf[0x7b] = 0x00;
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dev->pci_conf[0x80] = 0x00;
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dev->pci_conf[0x81] = 0x00;
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dev->pci_conf[0x82] = 0x00;
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dev->pci_conf[0x83] = 0x00;
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dev->pci_conf[0x84] = 0x00;
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dev->pci_conf[0x85] = 0x00;
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dev->pci_conf[0x86] = 0x00;
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dev->pci_conf[0x87] = 0x00;
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dev->pci_conf[0x8c] = 0x00;
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dev->pci_conf[0x8d] = 0x00;
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dev->pci_conf[0x8e] = 0x00;
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dev->pci_conf[0x8f] = 0x00;
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dev->pci_conf[0x90] = 0x00;
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dev->pci_conf[0x91] = 0x00;
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dev->pci_conf[0x92] = 0x00;
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dev->pci_conf[0x93] = 0x00;
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dev->pci_conf[0x93] = 0x00;
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dev->pci_conf[0x94] = 0x00;
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dev->pci_conf[0x95] = 0x00;
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dev->pci_conf[0x96] = 0x00;
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dev->pci_conf[0x97] = 0x00;
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dev->pci_conf[0x98] = 0x00;
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dev->pci_conf[0x99] = 0x00;
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dev->pci_conf[0x9a] = 0x00;
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dev->pci_conf[0x9b] = 0x00;
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dev->pci_conf[0x9c] = 0x00;
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dev->pci_conf[0x9d] = 0x00;
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dev->pci_conf[0x9e] = 0xff;
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dev->pci_conf[0x9f] = 0xff;
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dev->pci_conf[0xa0] = 0xff;
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dev->pci_conf[0xa1] = 0x00;
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dev->pci_conf[0xa2] = 0xff;
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dev->pci_conf[0xa3] = 0x00;
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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sis_5571_smram_recalc(dev);
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sis_5571_shadow_recalc(dev);
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flushmmucache();
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}
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static void
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sis_5571_host_to_pci_close(void *priv)
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{
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sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
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smram_del(dev->smram);
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free(dev);
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}
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static void *
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sis_5571_host_to_pci_init(UNUSED(const device_t *info))
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{
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sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) calloc(1, sizeof(sis_5571_host_to_pci_t));
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dev->sis = device_get_common_priv();
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/* SMRAM */
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dev->smram = smram_add();
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sis_5571_host_to_pci_reset(dev);
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return dev;
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}
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const device_t sis_5571_h2p_device = {
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.name = "SiS 5571 Host to PCI bridge",
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.internal_name = "sis_5571_host_to_pci",
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.flags = DEVICE_PCI,
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.local = 0x00,
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.init = sis_5571_host_to_pci_init,
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.close = sis_5571_host_to_pci_close,
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.reset = sis_5571_host_to_pci_reset,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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