582 lines
12 KiB
C
582 lines
12 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel 450KX Mars Chipset.
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*
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* Authors: Tiseno100,
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*
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* Copyright 2021 Tiseno100.
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*/
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/*
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Note: i450KX PB manages PCI memory access with MC manages DRAM memory access.
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Due to 86Box limitations we can't manage them seperately thus it is dev branch till then.
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i450GX is way more popular of an option but needs more stuff.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/smram.h>
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#include <86box/spd.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_450KX_LOG
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int i450kx_do_log = ENABLE_450KX_LOG;
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static void
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i450kx_log(const char *fmt, ...)
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{
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va_list ap;
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if (i450kx_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define i450kx_log(fmt, ...)
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#endif
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/* Shadow RAM Flags */
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#define LSB_DECISION (((shadow_value & 1) ? MEM_READ_EXTANY : MEM_READ_INTERNAL) | ((shadow_value & 2) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL))
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#define MSB_DECISION (((shadow_value & 0x10) ? MEM_READ_EXTANY : MEM_READ_INTERNAL) | ((shadow_value & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL))
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#define LSB_DECISION_MC (((shadow_value & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((shadow_value & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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#define MSB_DECISION_MC (((shadow_value & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((shadow_value & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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/* SMRAM */
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#define SMRAM_ADDR (((dev->pb_pci_conf[0xb9] << 8) | dev->pb_pci_conf[0xb8]) << 17)
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#define SMRAM_ADDR_MC (((dev->mc_pci_conf[0xb9] << 8) | dev->mc_pci_conf[0xb8]) << 16)
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#define SMRAM_SIZE (((dev->pb_pci_conf[0xbb] >> 4) + 1) * 64)
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#define SMRAM_SIZE_MC (((dev->mc_pci_conf[0xbb] >> 4) + 1) * 64)
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/* Miscellaneous */
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#define ENABLE_SEGMENT (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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#define DISABLE_SEGMENT (MEM_READ_DISABLED | MEM_WRITE_DISABLED)
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typedef struct i450kx_t {
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smram_t *smram;
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uint8_t pb_pci_conf[256], mc_pci_conf[256];
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} i450kx_t;
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static void
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i450kx_shadow(int is_mc, int cur_reg, uint8_t shadow_value, i450kx_t *dev)
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{
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if (cur_reg == 0x59) {
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mem_set_mem_state_both(0x80000, 0x20000, (is_mc) ? LSB_DECISION_MC : LSB_DECISION);
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mem_set_mem_state_both(0xf0000, 0x10000, (is_mc) ? MSB_DECISION_MC : MSB_DECISION);
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} else {
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mem_set_mem_state_both(0xc0000 + (((cur_reg & 7) - 2) * 0x8000), 0x4000, (is_mc) ? LSB_DECISION_MC : LSB_DECISION);
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mem_set_mem_state_both(0xc4000 + (((cur_reg & 7) - 2) * 0x8000), 0x4000, (is_mc) ? MSB_DECISION_MC : MSB_DECISION);
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}
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flushmmucache_nopc();
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}
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static void
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i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
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{
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smram_disable_all();
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if ((smram_addr != 0) && !!(dev->mc_pci_conf[0x57] & 8))
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smram_enable(dev->smram, smram_addr, smram_addr, smram_size, !!(dev->pb_pci_conf[0x57] & 8), 1);
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flushmmucache();
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}
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static void
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pb_write(int func, int addr, uint8_t val, void *priv)
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{
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i450kx_t *dev = (i450kx_t *)priv;
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switch (addr) {
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case 0x04:
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dev->pb_pci_conf[addr] &= val & 0xd7;
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break;
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case 0x06:
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dev->pb_pci_conf[addr] = val & 0x80;
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break;
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case 0x07:
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case 0x0d:
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dev->pb_pci_conf[addr] = val;
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break;
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case 0x0f:
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dev->pb_pci_conf[addr] = val & 0xcf;
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break;
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case 0x40:
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case 0x41:
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dev->pb_pci_conf[addr] = val;
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break;
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case 0x43:
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dev->pb_pci_conf[addr] = val & 0x80;
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break;
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case 0x48:
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dev->pb_pci_conf[addr] = val & 6;
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break;
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case 0x4a:
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case 0x4b:
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dev->pb_pci_conf[addr] = val;
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break;
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case 0x4c:
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dev->pb_pci_conf[addr] = val & 0xd8;
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break;
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case 0x53:
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dev->pb_pci_conf[addr] = val & 2;
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break;
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case 0x54:
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dev->pb_pci_conf[addr] = val & 0x7b;
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break;
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case 0x55:
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dev->pb_pci_conf[addr] = val & 2;
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break;
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case 0x57:
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dev->pb_pci_conf[addr] = val & 8;
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i450kx_smm(SMRAM_ADDR, SMRAM_SIZE, dev);
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break;
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case 0x58:
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dev->pb_pci_conf[addr] = val & 2;
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mem_set_mem_state_both(0xa0000, 0x20000, (val & 2) ? ENABLE_SEGMENT : DISABLE_SEGMENT);
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break;
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case 0x59:
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case 0x5a:
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case 0x5b:
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case 0x5c:
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case 0x5d:
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case 0x5e:
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case 0x5f:
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dev->pb_pci_conf[addr] = val & 0x33;
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i450kx_shadow(0, addr, val, dev);
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break;
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case 0x70:
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dev->pb_pci_conf[addr] = val & 0xfc;
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break;
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case 0x71:
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dev->pb_pci_conf[addr] = val & 0x71;
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break;
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case 0x78:
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dev->pb_pci_conf[addr] = val & 0xf0;
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break;
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case 0x79:
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dev->pb_pci_conf[addr] = val & 0xfc;
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break;
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case 0x7c:
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dev->pb_pci_conf[addr] = val & 0x5f;
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break;
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case 0x7d:
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dev->pb_pci_conf[addr] = val & 0x1a;
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break;
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case 0x7e:
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dev->pb_pci_conf[addr] = val & 0xf0;
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break;
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case 0x7f:
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case 0x88:
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case 0x89:
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case 0x8a:
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dev->pb_pci_conf[addr] = val;
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break;
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case 0x8b:
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dev->pb_pci_conf[addr] = val & 0x80;
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break;
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case 0x9c:
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dev->pb_pci_conf[addr] = val & 1;
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break;
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case 0xa4:
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dev->pb_pci_conf[addr] = val & 0xf9;
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break;
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case 0xa5:
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case 0xa6:
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dev->pb_pci_conf[addr] = val;
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break;
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case 0xa7:
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dev->pb_pci_conf[addr] = val & 0x0f;
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break;
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case 0xb0:
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dev->pb_pci_conf[addr] = val & 0xe0;
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break;
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case 0xb1:
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dev->pb_pci_conf[addr] = val & 0x1f;
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break;
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case 0xb4:
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dev->pb_pci_conf[addr] = val & 0xe8;
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break;
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case 0xb5:
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dev->pb_pci_conf[addr] = val & 0x1f;
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break;
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case 0xb8:
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case 0xb9:
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case 0xbb:
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dev->pb_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
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i450kx_smm(SMRAM_ADDR, SMRAM_SIZE, dev);
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break;
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case 0xc4:
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dev->pb_pci_conf[addr] = val & 5;
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break;
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case 0xc5:
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dev->pb_pci_conf[addr] = val & 0x0a;
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break;
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case 0xc6:
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dev->pb_pci_conf[addr] = val & 0x1d;
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break;
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case 0xc8:
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dev->pb_pci_conf[addr] = val & 0x1f;
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break;
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case 0xca:
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case 0xcb:
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dev->pb_pci_conf[addr] = val;
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break;
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}
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i450kx_log("i450KX-PB: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->pb_pci_conf[addr], inb(0x80));
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}
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static uint8_t
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pb_read(int func, int addr, void *priv)
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{
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i450kx_t *dev = (i450kx_t *)priv;
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return dev->pb_pci_conf[addr];
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}
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static void
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mc_write(int func, int addr, uint8_t val, void *priv)
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{
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i450kx_t *dev = (i450kx_t *)priv;
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switch (addr)
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{
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case 0x4c:
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dev->mc_pci_conf[addr] = val & 0xdf;
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break;
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case 0x4d:
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dev->mc_pci_conf[addr] = val & 0xdf;
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break;
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case 0x57:
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dev->mc_pci_conf[addr] = val & 8;
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i450kx_smm(SMRAM_ADDR, SMRAM_SIZE, dev);
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break;
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case 0x58:
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dev->mc_pci_conf[addr] = val & 2;
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break;
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case 0x59:
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case 0x5a:
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case 0x5b:
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case 0x5c:
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case 0x5d:
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case 0x5e:
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case 0x5f:
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dev->mc_pci_conf[addr] = val & 0x33;
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i450kx_shadow(1, addr, val, dev);
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break;
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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case 0x68:
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case 0x69:
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case 0x6a:
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case 0x6b:
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case 0x6c:
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case 0x6d:
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case 0x6e:
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case 0x6f:
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dev->mc_pci_conf[addr] = ((addr & 0x0f) % 2) ? 0 : (val & 0x7f);
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spd_write_drbs(dev->mc_pci_conf, 0x60, 0x6f, 4);
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break;
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case 0x74:
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case 0x75:
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case 0x76:
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case 0x77:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0x78:
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dev->mc_pci_conf[addr] = val & 0xf0;
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break;
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case 0x79:
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dev->mc_pci_conf[addr] = val & 0xfe;
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break;
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case 0x7a:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0x7b:
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dev->mc_pci_conf[addr] = val & 0x0f;
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break;
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case 0x7c:
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dev->mc_pci_conf[addr] = val & 0x1f;
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break;
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case 0x7d:
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dev->mc_pci_conf[addr] = val & 0x0c;
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break;
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case 0x7e:
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dev->mc_pci_conf[addr] = val & 0xf0;
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break;
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case 0x7f:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0x88:
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case 0x89:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0x8b:
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dev->mc_pci_conf[addr] = val & 0x80;
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break;
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case 0x8c:
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case 0x8d:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0xa4:
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dev->mc_pci_conf[addr] = val & 1;
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break;
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case 0xa5:
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dev->pb_pci_conf[addr] = val & 0xf0;
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break;
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case 0xa6:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0xa7:
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dev->mc_pci_conf[addr] = val & 0x0f;
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break;
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case 0xa8:
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dev->mc_pci_conf[addr] = val & 0xfe;
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break;
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case 0xa9:
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case 0xaa:
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case 0xab:
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case 0xac:
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case 0xad:
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case 0xae:
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dev->mc_pci_conf[addr] = val;
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break;
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case 0xaf:
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dev->mc_pci_conf[addr] = val & 0x7f;
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break;
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case 0xb8:
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case 0xb9:
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case 0xbb:
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dev->mc_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
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i450kx_smm(SMRAM_ADDR_MC, SMRAM_SIZE_MC, dev);
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break;
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case 0xbc:
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dev->mc_pci_conf[addr] = val & 1;
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break;
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case 0xc0:
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dev->mc_pci_conf[addr] = val & 7;
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break;
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case 0xc2:
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dev->mc_pci_conf[addr] = val & 3;
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break;
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case 0xc4:
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dev->mc_pci_conf[addr] = val & 0x3f;
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break;
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case 0xc6:
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dev->mc_pci_conf[addr] = val & 0x19;
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break;
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}
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i450kx_log("i450KX-MC: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->mc_pci_conf[addr], inb(0x80));
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}
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static uint8_t
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mc_read(int func, int addr, void *priv)
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{
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i450kx_t *dev = (i450kx_t *)priv;
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return dev->mc_pci_conf[addr];
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}
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static void
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i450kx_reset(void *priv)
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{
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i450kx_t *dev = (i450kx_t *)priv;
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/* CONFLICTS WARNING! We do not program anything on reset due to that */
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/* Defaults PB */
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dev->pb_pci_conf[0x00] = 0x86;
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dev->pb_pci_conf[0x01] = 0x80;
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dev->pb_pci_conf[0x02] = 0xc4;
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dev->pb_pci_conf[0x03] = 0x84;
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dev->pb_pci_conf[0x05] = 4;
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dev->pb_pci_conf[0x06] = 0x40;
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dev->pb_pci_conf[0x07] = 2;
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dev->pb_pci_conf[0x08] = 2;
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dev->pb_pci_conf[0x0b] = 6;
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dev->pb_pci_conf[0x0c] = 8;
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dev->pb_pci_conf[0x0d] = 0x20;
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dev->pb_pci_conf[0x49] = 0x14;
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dev->pb_pci_conf[0x4c] = 0x39;
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dev->pb_pci_conf[0x58] = 2;
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dev->pb_pci_conf[0x59] = 0x30;
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dev->pb_pci_conf[0x5a] = 0x33;
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dev->pb_pci_conf[0x5b] = 0x33;
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dev->pb_pci_conf[0x5c] = 0x33;
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dev->pb_pci_conf[0x5d] = 0x33;
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dev->pb_pci_conf[0x5e] = 0x33;
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dev->pb_pci_conf[0x5f] = 0x33;
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dev->pb_pci_conf[0xa4] = 1;
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dev->pb_pci_conf[0xa5] = 0xc0;
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dev->pb_pci_conf[0xa6] = 0xfe;
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dev->pb_pci_conf[0xc8] = 3;
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dev->pb_pci_conf[0xb8] = 5;
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|
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/* Defaults MC */
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dev->mc_pci_conf[0x00] = 0x86;
|
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dev->mc_pci_conf[0x01] = 0x80;
|
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dev->mc_pci_conf[0x02] = 0xc5;
|
|
dev->mc_pci_conf[0x03] = 0x84;
|
|
dev->mc_pci_conf[0x06] = 0x80;
|
|
dev->mc_pci_conf[0x08] = 4;
|
|
dev->mc_pci_conf[0x0b] = 5;
|
|
dev->mc_pci_conf[0x49] = 0x14;
|
|
dev->mc_pci_conf[0x4c] = 0x0b;
|
|
dev->mc_pci_conf[0x78] = 0x10;
|
|
dev->mc_pci_conf[0xa4] = 1;
|
|
dev->mc_pci_conf[0xa5] = 0xc0;
|
|
dev->mc_pci_conf[0xa6] = 0xfe;
|
|
dev->mc_pci_conf[0xac] = 0x16;
|
|
dev->mc_pci_conf[0xad] = 0x35;
|
|
dev->mc_pci_conf[0xae] = 0xdf;
|
|
dev->mc_pci_conf[0xaf] = 0x30;
|
|
dev->mc_pci_conf[0xb8] = 0x0a;
|
|
dev->mc_pci_conf[0xbc] = 1;
|
|
}
|
|
|
|
|
|
static void
|
|
i450kx_close(void *priv)
|
|
{
|
|
i450kx_t *dev = (i450kx_t *)priv;
|
|
|
|
smram_del(dev->smram);
|
|
free(dev);
|
|
}
|
|
|
|
|
|
static void *
|
|
i450kx_init(const device_t *info)
|
|
{
|
|
i450kx_t *dev = (i450kx_t *)malloc(sizeof(i450kx_t));
|
|
memset(dev, 0, sizeof(i450kx_t));
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev); /* Device 19: Intel 450KX PCI Bridge PB */
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, mc_read, mc_write, dev); /* Device 14: Intel 450KX Memory Controller MC */
|
|
|
|
dev->smram = smram_add();
|
|
|
|
cpu_cache_int_enabled = 1;
|
|
cpu_cache_ext_enabled = 1;
|
|
cpu_update_waitstates();
|
|
|
|
i450kx_reset(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
|
|
const device_t i450kx_device = {
|
|
"Intel 450KX (Mars)",
|
|
DEVICE_PCI,
|
|
0,
|
|
i450kx_init,
|
|
i450kx_close,
|
|
i450kx_reset,
|
|
{ NULL },
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|