232 lines
6.9 KiB
C
232 lines
6.9 KiB
C
#include "codegen_ops.h"
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/*Instruction has input dependency on register in REG field*/
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#define SRCDEP_REG (1ULL << 0)
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/*Instruction has input dependency on register in R/M field*/
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#define SRCDEP_RM (1ULL << 1)
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/*Instruction modifies register in REG field*/
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#define DSTDEP_REG (1ULL << 2)
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/*Instruction modifies register in R/M field*/
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#define DSTDEP_RM (1ULL << 3)
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#define SRCDEP_SHIFT 4
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#define DSTDEP_SHIFT 12
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/*Instruction has input dependency on given register*/
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#define SRCDEP_EAX (1ULL << 4)
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#define SRCDEP_ECX (1ULL << 5)
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#define SRCDEP_EDX (1ULL << 6)
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#define SRCDEP_EBX (1ULL << 7)
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#define SRCDEP_ESP (1ULL << 8)
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#define SRCDEP_EBP (1ULL << 9)
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#define SRCDEP_ESI (1ULL << 10)
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#define SRCDEP_EDI (1ULL << 11)
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/*Instruction modifies given register*/
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#define DSTDEP_EAX (1ULL << 12)
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#define DSTDEP_ECX (1ULL << 13)
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#define DSTDEP_EDX (1ULL << 14)
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#define DSTDEP_EBX (1ULL << 15)
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#define DSTDEP_ESP (1ULL << 16)
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#define DSTDEP_EBP (1ULL << 17)
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#define DSTDEP_ESI (1ULL << 18)
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#define DSTDEP_EDI (1ULL << 19)
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/*Instruction has ModR/M byte*/
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#define MODRM (1ULL << 20)
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/*Instruction implicitly uses ESP*/
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#define IMPL_ESP (1ULL << 21)
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/*Instruction is MMX shift or pack/unpack instruction*/
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#define MMX_SHIFTPACK (1ULL << 22)
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/*Instruction is MMX multiply instruction*/
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#define MMX_MULTIPLY (1ULL << 23)
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/*Instruction pops the FPU stack*/
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#define FPU_POP (1ULL << 24)
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/*Instruction pops the FPU stack twice*/
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#define FPU_POP2 (1ULL << 25)
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/*Instruction pushes onto the FPU stack*/
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#define FPU_PUSH (1ULL << 26)
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/*Instruction writes to ST(0)*/
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#define FPU_WRITE_ST0 (1ULL << 27)
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/*Instruction reads from ST(0)*/
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#define FPU_READ_ST0 (1ULL << 28)
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/*Instruction reads from and writes to ST(0)*/
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#define FPU_RW_ST0 (3ULL << 27)
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/*Instruction reads from ST(1)*/
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#define FPU_READ_ST1 (1ULL << 29)
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/*Instruction writes to ST(1)*/
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#define FPU_WRITE_ST1 (1ULL << 30)
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/*Instruction reads from and writes to ST(1)*/
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#define FPU_RW_ST1 (3ULL << 29)
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/*Instruction reads from ST(reg)*/
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#define FPU_READ_STREG (1ULL << 31)
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/*Instruction writes to ST(reg)*/
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#define FPU_WRITE_STREG (1ULL << 32)
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/*Instruction reads from and writes to ST(reg)*/
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#define FPU_RW_STREG (3ULL << 31)
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#define FPU_FXCH (1ULL << 33)
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#define HAS_IMM8 (1ULL << 34)
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#define HAS_IMM1632 (1ULL << 35)
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#define REGMASK_IMPL_ESP (1 << 8)
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#define REGMASK_SHIFTPACK (1 << 9)
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#define REGMASK_MULTIPLY (1 << 9)
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extern uint64_t opcode_deps[256];
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extern uint64_t opcode_deps_mod3[256];
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extern uint64_t opcode_deps_0f[256];
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extern uint64_t opcode_deps_0f_mod3[256];
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extern uint64_t opcode_deps_0f0f[256];
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extern uint64_t opcode_deps_0f0f_mod3[256];
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extern uint64_t opcode_deps_shift[8];
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extern uint64_t opcode_deps_shift_mod3[8];
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extern uint64_t opcode_deps_shift_cl[8];
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extern uint64_t opcode_deps_shift_cl_mod3[8];
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extern uint64_t opcode_deps_f6[8];
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extern uint64_t opcode_deps_f6_mod3[8];
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extern uint64_t opcode_deps_f7[8];
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extern uint64_t opcode_deps_f7_mod3[8];
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extern uint64_t opcode_deps_ff[8];
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extern uint64_t opcode_deps_ff_mod3[8];
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extern uint64_t opcode_deps_d8[8];
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extern uint64_t opcode_deps_d8_mod3[8];
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extern uint64_t opcode_deps_d9[8];
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extern uint64_t opcode_deps_d9_mod3[64];
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extern uint64_t opcode_deps_da[8];
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extern uint64_t opcode_deps_da_mod3[8];
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extern uint64_t opcode_deps_db[8];
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extern uint64_t opcode_deps_db_mod3[64];
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extern uint64_t opcode_deps_dc[8];
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extern uint64_t opcode_deps_dc_mod3[8];
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extern uint64_t opcode_deps_dd[8];
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extern uint64_t opcode_deps_dd_mod3[8];
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extern uint64_t opcode_deps_de[8];
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extern uint64_t opcode_deps_de_mod3[8];
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extern uint64_t opcode_deps_df[8];
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extern uint64_t opcode_deps_df_mod3[8];
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extern uint64_t opcode_deps_81[8];
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extern uint64_t opcode_deps_81_mod3[8];
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extern uint64_t opcode_deps_8x[8];
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extern uint64_t opcode_deps_8x_mod3[8];
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static inline uint32_t
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get_addr_regmask(uint64_t data, uint32_t fetchdat, int op_32)
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{
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uint32_t addr_regmask = 0;
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if (data & MODRM) {
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uint8_t modrm = fetchdat & 0xff;
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if ((modrm & 0xc0) != 0xc0) {
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if (op_32 & 0x200) {
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if ((modrm & 0x7) == 4) {
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uint8_t sib = (fetchdat >> 8) & 0xff;
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if ((modrm & 0xc0) != 0xc0 && (sib & 7) != 5) {
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addr_regmask = 1 << (sib & 7);
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if ((sib & 0x38) != 0x20)
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addr_regmask |= 1 << ((sib >> 3) & 7);
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}
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} else if ((modrm & 0xc7) != 5) {
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addr_regmask = 1 << (modrm & 7);
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}
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} else {
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if ((modrm & 0xc7) != 0x06) {
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switch (modrm & 7) {
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case 0:
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addr_regmask = REG_BX | REG_SI;
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break;
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case 1:
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addr_regmask = REG_BX | REG_DI;
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break;
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case 2:
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addr_regmask = REG_BP | REG_SI;
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break;
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case 3:
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addr_regmask = REG_BP | REG_DI;
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break;
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case 4:
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addr_regmask = REG_SI;
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break;
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case 5:
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addr_regmask = REG_DI;
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break;
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case 6:
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addr_regmask = REG_BP;
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break;
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case 7:
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addr_regmask = REG_BX;
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break;
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}
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}
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}
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}
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}
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if (data & IMPL_ESP)
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addr_regmask |= REGMASK_IMPL_ESP;
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return addr_regmask;
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}
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static inline uint32_t
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get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit8, int op_32)
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{
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uint32_t mask = 0;
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if (data & SRCDEP_REG) {
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int reg = (fetchdat >> 3) & 7;
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if (bit8)
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reg &= 3;
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mask |= (1 << reg);
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}
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if (data & SRCDEP_RM) {
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int reg = fetchdat & 7;
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if (bit8)
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reg &= 3;
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mask |= (1 << reg);
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}
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mask |= ((data >> SRCDEP_SHIFT) & 0xff);
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if (data & MMX_SHIFTPACK)
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mask |= REGMASK_SHIFTPACK;
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if (data & MMX_MULTIPLY)
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mask |= REGMASK_MULTIPLY;
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mask |= get_addr_regmask(data, fetchdat, op_32);
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return mask;
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}
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static inline uint32_t
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get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit8)
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{
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uint32_t mask = 0;
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if (data & DSTDEP_REG) {
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int reg = (fetchdat >> 3) & 7;
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if (bit8)
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reg &= 3;
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mask |= (1 << reg);
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}
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if (data & DSTDEP_RM) {
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int reg = fetchdat & 7;
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if (bit8)
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reg &= 3;
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mask |= (1 << reg);
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}
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mask |= ((data >> DSTDEP_SHIFT) & 0xff);
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if (data & MMX_SHIFTPACK)
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mask |= REGMASK_SHIFTPACK;
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if (data & MMX_MULTIPLY)
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mask |= REGMASK_MULTIPLY;
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if (data & IMPL_ESP)
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mask |= REGMASK_IMPL_ESP | (1 << REG_ESP);
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return mask;
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}
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