982 lines
33 KiB
C
982 lines
33 KiB
C
#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include <math.h>
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#ifndef INFINITY
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# define INFINITY (__builtin_inff())
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#endif
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#include "../86box.h"
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#include "cpu.h"
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#include "x86.h"
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#include "x86_ops.h"
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#include "x87.h"
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#include "../io.h"
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#include "../mem.h"
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#include "../nmi.h"
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#include "../pic.h"
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#include "../timer.h"
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#include "../floppy/floppy.h"
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#include "../floppy/fdc.h"
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#ifdef USE_DYNAREC
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#include "codegen.h"
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#endif
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#include "386_common.h"
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#define CPU_BLOCK_END() cpu_block_end = 1
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uint32_t cpu_cur_status = 0;
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int cpu_reps, cpu_reps_latched;
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int cpu_notreps, cpu_notreps_latched;
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int inrecomp = 0;
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int cpu_recomp_blocks, cpu_recomp_full_ins, cpu_new_blocks;
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int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latched, cpu_new_blocks_latched;
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int cpu_block_end = 0;
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int nmi_enable = 1;
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int inscounts[256];
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uint32_t oldpc2;
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int trap;
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int cpl_override=0;
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int fpucount=0;
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uint16_t rds;
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uint16_t ea_rseg;
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int cgate32;
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uint32_t rmdat32;
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uint32_t backupregs[16];
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int oddeven=0;
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int inttype;
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uint32_t oldcs2;
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uint32_t oldecx;
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uint32_t *eal_r, *eal_w;
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uint16_t *mod1add[2][8];
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uint32_t *mod1seg[8];
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static __inline void fetch_ea_32_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = cpu_state.ea_seg->base;
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ea_rseg = cpu_state.ea_seg->seg;
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if (cpu_rm == 4)
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{
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uint8_t sib = rmdat >> 8;
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switch (cpu_mod)
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{
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case 0:
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cpu_state.eaaddr = cpu_state.regs[sib & 7].l;
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cpu_state.pc++;
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break;
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case 1:
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cpu_state.pc++;
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cpu_state.eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
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break;
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case 2:
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cpu_state.eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
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cpu_state.pc += 5;
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break;
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}
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/*SIB byte present*/
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if ((sib & 7) == 5 && !cpu_mod)
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cpu_state.eaaddr = getlong();
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else if ((sib & 6) == 4 && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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cpu_state.ea_seg = &_ss;
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}
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if (((sib >> 3) & 7) != 4)
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cpu_state.eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
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}
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else
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{
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cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
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if (cpu_mod)
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{
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if (cpu_rm == 5 && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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cpu_state.ea_seg = &_ss;
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}
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if (cpu_mod == 1)
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{
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cpu_state.eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.pc++;
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}
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else
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{
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cpu_state.eaaddr += getlong();
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}
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}
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else if (cpu_rm == 5)
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{
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cpu_state.eaaddr = getlong();
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}
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}
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
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}
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cpu_state.last_ea = cpu_state.eaaddr;
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}
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static __inline void fetch_ea_16_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = cpu_state.ea_seg->base;
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ea_rseg = cpu_state.ea_seg->seg;
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if (!cpu_mod && cpu_rm == 6)
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{
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cpu_state.eaaddr = getword();
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}
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else
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{
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switch (cpu_mod)
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{
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case 0:
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cpu_state.eaaddr = 0;
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break;
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case 1:
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cpu_state.eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
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break;
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case 2:
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cpu_state.eaaddr = getword();
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break;
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}
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cpu_state.eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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cpu_state.ea_seg = &_ss;
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}
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cpu_state.eaaddr &= 0xFFFF;
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}
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
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}
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cpu_state.last_ea = cpu_state.eaaddr;
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}
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#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (cpu_state.abrt) return 1; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (cpu_state.abrt) return 1
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#include "x86_flags.h"
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void x86_int(int num)
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{
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uint32_t addr;
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flags_rebuild();
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cpu_state.pc=cpu_state.oldpc;
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if (msw&1)
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{
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pmodeint(num,0);
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}
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else
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{
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addr = (num << 2) + idt.base;
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if (addr + 3 > idt.limit)
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{
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if(idt.limit < 35)
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{
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cpu_state.abrt = 0;
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softresetx86();
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cpu_set_edx();
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pclog("IDT limit is less than 35 in real mode - reset\n");
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}
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else x86_int(8);
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return;
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}
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if (stack32)
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{
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writememw(ss,ESP-2,flags);
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writememw(ss,ESP-4,CS);
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writememw(ss,ESP-6,cpu_state.pc);
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ESP-=6;
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}
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else
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{
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writememw(ss,((SP-2)&0xFFFF),flags);
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writememw(ss,((SP-4)&0xFFFF),CS);
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writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
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SP-=6;
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}
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flags&=~I_FLAG;
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flags&=~T_FLAG;
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oxpc=cpu_state.pc;
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cpu_state.pc=readmemw(0,addr);
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loadcs(readmemw(0,addr+2));
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}
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cycles-=70;
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CPU_BLOCK_END();
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}
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void x86_int_sw(int num)
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{
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uint32_t addr;
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flags_rebuild();
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cycles -= timing_int;
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if (msw&1)
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{
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pmodeint(num,1);
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}
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else
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{
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addr = (num << 2) + idt.base;
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if (addr + 3 > idt.limit)
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{
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x86_int(13);
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return;
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}
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if (stack32)
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{
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writememw(ss,ESP-2,flags);
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writememw(ss,ESP-4,CS);
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writememw(ss,ESP-6,cpu_state.pc);
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ESP-=6;
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}
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else
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{
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writememw(ss,((SP-2)&0xFFFF),flags);
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writememw(ss,((SP-4)&0xFFFF),CS);
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writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
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SP-=6;
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}
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flags&=~I_FLAG;
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flags&=~T_FLAG;
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oxpc=cpu_state.pc;
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cpu_state.pc=readmemw(0,addr);
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loadcs(readmemw(0,addr+2));
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cycles -= timing_int_rm;
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}
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trap = 0;
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CPU_BLOCK_END();
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}
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int x86_int_sw_rm(int num)
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{
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uint32_t addr;
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uint16_t new_pc, new_cs;
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flags_rebuild();
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cycles -= timing_int;
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addr = num << 2;
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new_pc = readmemw(0, addr);
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new_cs = readmemw(0, addr + 2);
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if (cpu_state.abrt) return 1;
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writememw(ss,((SP-2)&0xFFFF),flags); if (cpu_state.abrt) {pclog("abrt5\n"); return 1; }
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writememw(ss,((SP-4)&0xFFFF),CS);
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writememw(ss,((SP-6)&0xFFFF),cpu_state.pc); if (cpu_state.abrt) {pclog("abrt6\n"); return 1; }
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SP-=6;
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eflags &= ~VIF_FLAG;
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flags &= ~T_FLAG;
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cpu_state.pc = new_pc;
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loadcs(new_cs);
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oxpc=cpu_state.pc;
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cycles -= timing_int_rm;
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trap = 0;
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CPU_BLOCK_END();
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return 0;
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}
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void x86illegal()
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{
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x86_int(6);
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}
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/*Prefetch emulation is a fairly simplistic model:
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- All instruction bytes must be fetched before it starts.
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- Cycles used for non-instruction memory accesses are counted and subtracted
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from the total cycles taken
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- Any remaining cycles are used to refill the prefetch queue.
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Note that this is only used for 286 / 386 systems. It is disabled when the
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internal cache on 486+ CPUs is enabled.
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*/
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static int prefetch_bytes = 0;
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static int prefetch_prefixes = 0;
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static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int reads_l, int writes, int writes_l, int ea32)
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{
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int mem_cycles = reads*cpu_cycles_read + reads_l*cpu_cycles_read_l + writes*cpu_cycles_write + writes_l*cpu_cycles_write_l;
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if (instr_cycles < mem_cycles)
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instr_cycles = mem_cycles;
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prefetch_bytes -= prefetch_prefixes;
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prefetch_bytes -= bytes;
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if (modrm != -1)
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{
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if (ea32)
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{
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if ((modrm & 7) == 4)
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{
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if ((modrm & 0x700) == 0x500)
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prefetch_bytes -= 5;
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else if ((modrm & 0xc0) == 0x40)
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prefetch_bytes -= 2;
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else if ((modrm & 0xc0) == 0x80)
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prefetch_bytes -= 5;
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}
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else
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{
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if ((modrm & 0xc7) == 0x05)
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prefetch_bytes -= 4;
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else if ((modrm & 0xc0) == 0x40)
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prefetch_bytes--;
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else if ((modrm & 0xc0) == 0x80)
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prefetch_bytes -= 4;
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}
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}
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else
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{
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if ((modrm & 0xc7) == 0x06)
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prefetch_bytes -= 2;
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else if ((modrm & 0xc0) != 0xc0)
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prefetch_bytes -= ((modrm & 0xc0) >> 6);
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}
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}
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/* Fill up prefetch queue */
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while (prefetch_bytes < 0)
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{
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prefetch_bytes += cpu_prefetch_width;
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cycles -= cpu_prefetch_cycles;
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}
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/* Subtract cycles used for memory access by instruction */
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instr_cycles -= mem_cycles;
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while (instr_cycles >= cpu_prefetch_cycles)
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{
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prefetch_bytes += cpu_prefetch_width;
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instr_cycles -= cpu_prefetch_cycles;
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}
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prefetch_prefixes = 0;
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}
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static void prefetch_flush()
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{
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prefetch_bytes = 0;
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}
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#define PREFETCH_RUN(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32) \
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do { if (cpu_prefetch_cycles) prefetch_run(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32); } while (0)
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#define PREFETCH_PREFIX() do { if (cpu_prefetch_cycles) prefetch_prefixes++; } while (0)
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#define PREFETCH_FLUSH() prefetch_flush()
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int checkio(int port)
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{
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uint16_t t;
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uint8_t d;
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cpl_override = 1;
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t = readmemw(tr.base, 0x66);
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cpl_override = 0;
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if (cpu_state.abrt) return 0;
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if ((t+(port>>3))>tr.limit) return 1;
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cpl_override = 1;
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d = readmemb386l(0, tr.base + t + (port >> 3));
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cpl_override = 0;
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return d&(1<<(port&7));
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}
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int xout=0;
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#if 0
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#define divexcp() { \
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pclog("Divide exception at %04X(%06X):%04X\n",CS,cs,cpu_state.pc); \
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x86_int(0); \
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}
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#endif
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#define divexcp() { \
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x86_int(0); \
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}
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int divl(uint32_t val)
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{
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uint64_t num, quo;
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uint32_t rem, quo32;
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if (val==0)
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{
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divexcp();
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return 1;
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}
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num=(((uint64_t)EDX)<<32)|EAX;
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quo=num/val;
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rem=num%val;
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quo32=(uint32_t)(quo&0xFFFFFFFF);
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if (quo!=(uint64_t)quo32)
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{
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divexcp();
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return 1;
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}
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EDX=rem;
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EAX=quo32;
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return 0;
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}
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int idivl(int32_t val)
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{
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int64_t num, quo;
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int32_t rem, quo32;
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if (val==0)
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{
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divexcp();
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return 1;
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}
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num=(((uint64_t)EDX)<<32)|EAX;
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quo=num/val;
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rem=num%val;
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quo32=(int32_t)(quo&0xFFFFFFFF);
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if (quo!=(int64_t)quo32)
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{
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divexcp();
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return 1;
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}
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EDX=rem;
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EAX=quo32;
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return 0;
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}
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void cpu_386_flags_extract()
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{
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flags_extract();
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}
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void cpu_386_flags_rebuild()
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{
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flags_rebuild();
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}
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int oldi;
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uint32_t testr[9];
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int dontprint=0;
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#define OP_TABLE(name) ops_ ## name
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#define CLOCK_CYCLES(c) cycles -= (c)
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#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
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#include "386_ops.h"
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#define CACHE_ON() (!(cr0 & (1 << 30)) /*&& (cr0 & 1)*/ && !(flags & T_FLAG))
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#ifdef USE_DYNAREC
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static int cpu_cycle_period(void)
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{
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switch(cpu_pci_speed)
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{
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case 333333333:
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return is_pentium ? 1000 : 1333;
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break;
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default:
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return 1000;
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break;
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}
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}
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static int cycles_main = 0;
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void exec386_dynarec(int cycs)
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{
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uint8_t temp;
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uint32_t addr;
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int tempi;
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int cycdiff;
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int oldcyc;
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uint32_t start_pc = 0;
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cycles_main += cycs;
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while (cycles_main > 0)
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{
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int cycles_start;
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#if 0
|
|
switch(cpu_pci_speed)
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|
{
|
|
case 16000000:
|
|
cycles += 640;
|
|
break;
|
|
case 20000000:
|
|
cycles += 800;
|
|
break;
|
|
case 25000000:
|
|
default:
|
|
cycles += 1000;
|
|
break;
|
|
case 27500000:
|
|
cycles += 1100;
|
|
break;
|
|
case 30000000:
|
|
cycles += 1200;
|
|
break;
|
|
case 333333333:
|
|
cycles += 1333;
|
|
break;
|
|
case 37500000:
|
|
cycles += 1500;
|
|
break;
|
|
case 40000000:
|
|
cycles += 1600;
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|
break;
|
|
case 41666667:
|
|
cycles += 1666;
|
|
break;
|
|
}
|
|
#endif
|
|
cycles += cpu_cycle_period();
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|
|
|
cycles_start = cycles;
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|
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|
timer_start_period(cycles << TIMER_SHIFT);
|
|
while (cycles>0)
|
|
{
|
|
oldcs = CS;
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|
cpu_state.oldpc = cpu_state.pc;
|
|
oldcpl = CPL;
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cpu_state.op32 = use32;
|
|
|
|
|
|
cycdiff=0;
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|
oldcyc=cycles;
|
|
if (!CACHE_ON()) /*Interpret block*/
|
|
{
|
|
cpu_block_end = 0;
|
|
while (!cpu_block_end)
|
|
{
|
|
oldcs=CS;
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
oldcpl=CPL;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
if (!cpu_state.abrt)
|
|
{
|
|
trap = flags & T_FLAG;
|
|
opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
|
|
cpu_state.pc++;
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
}
|
|
|
|
if (!use32) cpu_state.pc &= 0xffff;
|
|
|
|
if (((cs + cpu_state.pc) >> 12) != pccache)
|
|
CPU_BLOCK_END();
|
|
|
|
/* if (ssegs)
|
|
{
|
|
ds=oldds;
|
|
ss=oldss;
|
|
ssegs=0;
|
|
}*/
|
|
if (cpu_state.abrt)
|
|
CPU_BLOCK_END();
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
ins++;
|
|
insc++;
|
|
|
|
/* if ((cs + pc) == 4)
|
|
fatal("4\n");*/
|
|
/* if (ins >= 141400000)
|
|
output = 3;*/
|
|
}
|
|
}
|
|
else
|
|
{
|
|
uint32_t phys_addr = get_phys(cs+cpu_state.pc);
|
|
int hash = HASH(phys_addr);
|
|
codeblock_t *block = codeblock_hash[hash];
|
|
int valid_block = 0;
|
|
trap = 0;
|
|
|
|
if (block && !cpu_state.abrt)
|
|
{
|
|
page_t *page = &pages[phys_addr >> 12];
|
|
|
|
/*Block must match current CS, PC, code segment size,
|
|
and physical address. The physical address check will
|
|
also catch any page faults at this stage*/
|
|
valid_block = (block->pc == cs + cpu_state.pc) && (block->_cs == cs) &&
|
|
(block->phys == phys_addr) && !((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
|
|
((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
|
|
if (!valid_block)
|
|
{
|
|
uint64_t mask = (uint64_t)1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
|
|
|
|
if (page->code_present_mask[(phys_addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] & mask)
|
|
{
|
|
/*Walk page tree to see if we find the correct block*/
|
|
codeblock_t *new_block = codeblock_tree_find(phys_addr, cs);
|
|
if (new_block)
|
|
{
|
|
valid_block = (new_block->pc == cs + cpu_state.pc) && (new_block->_cs == cs) &&
|
|
(new_block->phys == phys_addr) && !((new_block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
|
|
((new_block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
|
|
if (valid_block)
|
|
block = new_block;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (valid_block && (block->page_mask & *block->dirty_mask))
|
|
{
|
|
codegen_check_flush(page, page->dirty_mask[(phys_addr >> 10) & 3], phys_addr);
|
|
page->dirty_mask[(phys_addr >> 10) & 3] = 0;
|
|
if (!block->valid)
|
|
valid_block = 0;
|
|
}
|
|
if (valid_block && block->page_mask2)
|
|
{
|
|
/*We don't want the second page to cause a page
|
|
fault at this stage - that would break any
|
|
code crossing a page boundary where the first
|
|
page is present but the second isn't. Instead
|
|
allow the first page to be interpreted and for
|
|
the page fault to occur when the page boundary
|
|
is actually crossed.*/
|
|
uint32_t phys_addr_2 = get_phys_noabrt(block->endpc);
|
|
page_t *page_2 = &pages[phys_addr_2 >> 12];
|
|
|
|
if ((block->phys_2 ^ phys_addr_2) & ~0xfff)
|
|
valid_block = 0;
|
|
else if (block->page_mask2 & *block->dirty_mask2)
|
|
{
|
|
codegen_check_flush(page_2, page_2->dirty_mask[(phys_addr_2 >> 10) & 3], phys_addr_2);
|
|
page_2->dirty_mask[(phys_addr_2 >> 10) & 3] = 0;
|
|
if (!block->valid)
|
|
valid_block = 0;
|
|
}
|
|
}
|
|
if (valid_block && block->was_recompiled && (block->flags & CODEBLOCK_STATIC_TOP) && block->TOP != cpu_state.TOP)
|
|
{
|
|
/*FPU top-of-stack does not match the value this block was compiled
|
|
with, re-compile using dynamic top-of-stack*/
|
|
block->flags &= ~CODEBLOCK_STATIC_TOP;
|
|
block->was_recompiled = 0;
|
|
}
|
|
}
|
|
|
|
if (valid_block && block->was_recompiled)
|
|
{
|
|
void (*code)() = (void *)&block->data[BLOCK_START];
|
|
|
|
codeblock_hash[hash] = block;
|
|
|
|
inrecomp=1;
|
|
code();
|
|
inrecomp=0;
|
|
if (!use32) cpu_state.pc &= 0xffff;
|
|
cpu_recomp_blocks++;
|
|
/* ins += codeblock_ins[index];
|
|
insc += codeblock_ins[index];*/
|
|
/* pclog("Exit block now %04X:%04X\n", CS, pc);*/
|
|
}
|
|
else if (valid_block && !cpu_state.abrt)
|
|
{
|
|
start_pc = cpu_state.pc;
|
|
|
|
cpu_block_end = 0;
|
|
x86_was_reset = 0;
|
|
|
|
cpu_new_blocks++;
|
|
|
|
codegen_block_start_recompile(block);
|
|
codegen_in_recompile = 1;
|
|
|
|
while (!cpu_block_end)
|
|
{
|
|
oldcs=CS;
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
oldcpl=CPL;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
if (!cpu_state.abrt)
|
|
{
|
|
trap = flags & T_FLAG;
|
|
opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
|
|
cpu_state.pc++;
|
|
|
|
codegen_generate_call(opcode, x86_opcodes[(opcode | cpu_state.op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
|
|
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
|
|
if (x86_was_reset)
|
|
break;
|
|
}
|
|
|
|
if (!use32) cpu_state.pc &= 0xffff;
|
|
|
|
/*Cap source code at 4000 bytes per block; this
|
|
will prevent any block from spanning more than
|
|
2 pages. In practice this limit will never be
|
|
hit, as host block size is only 2kB*/
|
|
if ((cpu_state.pc - start_pc) > 1000)
|
|
CPU_BLOCK_END();
|
|
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
codegen_block_remove();
|
|
CPU_BLOCK_END();
|
|
}
|
|
|
|
ins++;
|
|
insc++;
|
|
}
|
|
|
|
if (!cpu_state.abrt && !x86_was_reset)
|
|
codegen_block_end_recompile(block);
|
|
|
|
if (x86_was_reset)
|
|
codegen_reset();
|
|
|
|
codegen_in_recompile = 0;
|
|
}
|
|
else if (!cpu_state.abrt)
|
|
{
|
|
/*Mark block but do not recompile*/
|
|
start_pc = cpu_state.pc;
|
|
|
|
cpu_block_end = 0;
|
|
x86_was_reset = 0;
|
|
|
|
codegen_block_init(phys_addr);
|
|
|
|
while (!cpu_block_end)
|
|
{
|
|
oldcs=CS;
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
oldcpl=CPL;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
codegen_endpc = (cs + cpu_state.pc) + 8;
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
|
|
if (!cpu_state.abrt)
|
|
{
|
|
trap = flags & T_FLAG;
|
|
opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
|
|
cpu_state.pc++;
|
|
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
|
|
if (x86_was_reset)
|
|
break;
|
|
}
|
|
|
|
if (!use32) cpu_state.pc &= 0xffff;
|
|
|
|
/*Cap source code at 4000 bytes per block; this
|
|
will prevent any block from spanning more than
|
|
2 pages. In practice this limit will never be
|
|
hit, as host block size is only 2kB*/
|
|
if ((cpu_state.pc - start_pc) > 1000)
|
|
CPU_BLOCK_END();
|
|
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
codegen_block_remove();
|
|
CPU_BLOCK_END();
|
|
}
|
|
|
|
ins++;
|
|
insc++;
|
|
}
|
|
|
|
if (!cpu_state.abrt && !x86_was_reset)
|
|
codegen_block_end();
|
|
|
|
if (x86_was_reset)
|
|
codegen_reset();
|
|
}
|
|
}
|
|
|
|
cycdiff=oldcyc-cycles;
|
|
tsc += cycdiff;
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
flags_rebuild();
|
|
tempi = cpu_state.abrt;
|
|
cpu_state.abrt = 0;
|
|
x86_doabrt(tempi);
|
|
if (cpu_state.abrt)
|
|
{
|
|
cpu_state.abrt = 0;
|
|
CS = oldcs;
|
|
cpu_state.pc = cpu_state.oldpc;
|
|
pclog("Double fault %i\n", ins);
|
|
pmodeint(8, 0);
|
|
if (cpu_state.abrt)
|
|
{
|
|
cpu_state.abrt = 0;
|
|
softresetx86();
|
|
cpu_set_edx();
|
|
pclog("Triple fault - reset\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
if (trap)
|
|
{
|
|
|
|
flags_rebuild();
|
|
if (msw&1)
|
|
{
|
|
pmodeint(1,0);
|
|
}
|
|
else
|
|
{
|
|
writememw(ss,(SP-2)&0xFFFF,flags);
|
|
writememw(ss,(SP-4)&0xFFFF,CS);
|
|
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
|
|
SP-=6;
|
|
addr = (1 << 2) + idt.base;
|
|
flags&=~I_FLAG;
|
|
flags&=~T_FLAG;
|
|
cpu_state.pc=readmemw(0,addr);
|
|
loadcs(readmemw(0,addr+2));
|
|
}
|
|
}
|
|
else if (nmi && nmi_enable && nmi_mask)
|
|
{
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
oldcs = CS;
|
|
pclog("NMI\n");
|
|
x86_int(2);
|
|
nmi_enable = 0;
|
|
if (nmi_auto_clear)
|
|
{
|
|
nmi_auto_clear = 0;
|
|
nmi = 0;
|
|
}
|
|
}
|
|
else if ((flags&I_FLAG) && pic_intpending)
|
|
{
|
|
temp=picinterrupt();
|
|
if (temp!=0xFF)
|
|
{
|
|
CPU_BLOCK_END();
|
|
flags_rebuild();
|
|
if (msw&1)
|
|
{
|
|
/* if (temp == 0x0E)
|
|
{
|
|
pclog("Servicing FDC interupt (p)!\n");
|
|
} */
|
|
pmodeint(temp,0);
|
|
}
|
|
else
|
|
{
|
|
/* if (temp == 0x0E)
|
|
{
|
|
pclog("Servicing FDC interupt (r)!\n");
|
|
} */
|
|
writememw(ss,(SP-2)&0xFFFF,flags);
|
|
writememw(ss,(SP-4)&0xFFFF,CS);
|
|
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
|
|
SP-=6;
|
|
addr=temp<<2;
|
|
flags&=~I_FLAG;
|
|
flags&=~T_FLAG;
|
|
oxpc=cpu_state.pc;
|
|
cpu_state.pc=readmemw(0,addr);
|
|
loadcs(readmemw(0,addr+2));
|
|
}
|
|
}
|
|
/* else
|
|
{
|
|
pclog("Servicing pending interrupt 0xFF (!)!\n");
|
|
} */
|
|
}
|
|
}
|
|
timer_end_period(cycles << TIMER_SHIFT);
|
|
cycles_main -= (cycles_start - cycles);
|
|
}
|
|
}
|
|
#endif
|