7c67e867c8
IBM.H is gone, video stuff re-organized. Keyboard stuff reorganized. Machines that have their own video, mouse and/or keyboard now have all this in their machine file. Fixed and other cleanups here and there.
1075 lines
32 KiB
C
1075 lines
32 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Driver for IBM PS/2 ESDI disk controller (MCA)
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*
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* AdapterID: 0xDDFF
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* AdapterName: "ESDI Fixed Disk Controller"
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* NumBytes 2
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* I/O base: 0x3510-0x3517
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* IRQ: 14
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*
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* Primary Board pos[0]=XXxx xx0X 0x3510
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* Secondary Board pos[0]=XXxx xx1X 0x3518
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*
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* DMA 5 pos[0]=XX01 01XX
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* DMA 6 pos[0]=XX01 10XX
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* DMA 7 pos[0]=XX01 11XX
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* DMA 0 pos[0]=XX00 00XX
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* DMA 1 pos[0]=XX00 01XX
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* DMA 3 pos[0]=XX00 11XX
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* DMA 4 pos[0]=XX01 00XX
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*
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* MCA Fairness ON pos[0]=X1XX XXXX
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* MCA Fairness OFF pos[0]=X0XX XXXX
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*
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* ROM C000 pos[1]=XXXX 0000
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* ROM C400 pos[1]=XXXX 0001
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* ROM C800 pos[1]=XXXX 0010
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* ROM CC00 pos[1]=XXXX 0011
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* ROM D000 pos[1]=XXXX 0100
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* ROM D400 pos[1]=XXXX 0101
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* ROM D800 pos[1]=XXXX 0110
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* ROM DC00 pos[1]=XXXX 0111
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* ROM Disabled pos[1]=XXXX 1XXX
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*
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* DMA Burst 8 pos[1]=XX01 XXXX
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* DMA Burst 16 pos[1]=XX10 XXXX
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* DMA Burst 24 pos[1]=XX11 XXXX
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* DMA Disabled pos[1]=XX00 XXXX
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*
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* Although this is an MCA device, meaning that the system
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* software will take care of device configuration, the ESDI
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* controller is a somewhat weird one.. it's I/O base address
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* and IRQ channel are locked to 0x3510 and IRQ14, possibly
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* to enforce compatibility with the IBM MFM disk controller
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* that was also in use on these systems. All other settings,
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* however, are auto-configured by the system software as
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* shown above.
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*
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* Version: @(#)hdc_esdi_mca.c 1.0.8 2017/11/04
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2008-2017 Sarah Walker.
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* Copyright 2017 Fred N. van Kempen.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../device.h"
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#include "../dma.h"
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#include "../io.h"
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#include "../mca.h"
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#include "../mem.h"
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#include "../pic.h"
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#include "../rom.h"
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#include "../timer.h"
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#include "../ui.h"
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#include "hdc.h"
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#include "hdd.h"
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/* These are hardwired. */
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#define ESDI_IOADDR_PRI 0x3510
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#define ESDI_IOADDR_SEC 0x3518
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#define ESDI_IRQCHAN 14
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#define BIOS_FILE_L L"roms/hdd/esdi/90x8969.bin"
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#define BIOS_FILE_H L"roms/hdd/esdi/90x8970.bin"
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#define ESDI_TIME (200LL*TIMER_USEC)
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#define CMD_ADAPTER 0
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typedef struct esdi_drive {
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int spt, hpc;
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int tracks;
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int sectors;
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int present;
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int hdd_num;
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} drive_t;
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typedef struct esdi {
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uint16_t base;
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int8_t irq;
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int8_t dma;
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uint32_t bios;
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rom_t bios_rom;
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uint8_t basic_ctrl;
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uint8_t status;
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uint8_t irq_status;
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int irq_in_progress;
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int cmd_req_in_progress;
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int cmd_pos;
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uint16_t cmd_data[4];
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int cmd_dev;
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int status_pos,
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status_len;
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uint16_t status_data[256];
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int data_pos;
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uint16_t data[256];
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uint16_t sector_buffer[256][256];
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int sector_pos;
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int sector_count;
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int command;
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int cmd_state;
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int in_reset;
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int64_t callback;
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uint32_t rba;
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struct {
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int req_in_progress;
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} cmds[3];
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drive_t drives[2];
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uint8_t pos_regs[8];
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} esdi_t;
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#define STATUS_DMA_ENA (1 << 7)
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#define STATUS_IRQ_PENDING (1 << 6)
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#define STATUS_CMD_IN_PROGRESS (1 << 5)
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#define STATUS_BUSY (1 << 4)
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#define STATUS_STATUS_OUT_FULL (1 << 3)
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#define STATUS_CMD_IR_FULL (1 << 2)
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#define STATUS_TRANSFER_REQ (1 << 1)
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#define STATUS_IRQ (1 << 0)
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#define CTRL_RESET (1 << 7)
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#define CTRL_DMA_ENA (1 << 1)
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#define CTRL_IRQ_ENA (1 << 0)
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#define IRQ_HOST_ADAPTER (7 << 5)
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#define IRQ_DEVICE_0 (0 << 5)
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#define IRQ_CMD_COMPLETE_SUCCESS 0x1
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#define IRQ_RESET_COMPLETE 0xa
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#define IRQ_DATA_TRANSFER_READY 0xb
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#define IRQ_CMD_COMPLETE_FAILURE 0xc
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#define ATTN_DEVICE_SEL (7 << 5)
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#define ATTN_HOST_ADAPTER (7 << 5)
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#define ATTN_DEVICE_0 (0 << 5)
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#define ATTN_DEVICE_1 (1 << 5)
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#define ATTN_REQ_MASK 0x0f
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#define ATTN_CMD_REQ 1
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#define ATTN_EOI 2
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#define ATTN_RESET 4
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#define CMD_SIZE_4 (1 << 14)
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#define CMD_DEVICE_SEL (7 << 5)
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#define CMD_MASK 0x1f
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#define CMD_READ 0x01
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#define CMD_WRITE 0x02
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#define CMD_READ_VERIFY 0x03
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#define CMD_WRITE_VERIFY 0x04
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#define CMD_SEEK 0x05
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#define CMD_GET_DEV_CONFIG 0x09
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#define CMD_GET_POS_INFO 0x0a
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#define STATUS_LEN(x) ((x) << 8)
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#define STATUS_DEVICE_HOST_ADAPTER (7 << 5)
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static __inline void
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set_irq(esdi_t *dev)
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{
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if (dev->basic_ctrl & CTRL_IRQ_ENA)
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picint(1 << dev->irq);
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}
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static __inline void
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clear_irq(esdi_t *dev)
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{
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picintc(1 << dev->irq);
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}
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static void
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cmd_unsupported(esdi_t *dev)
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{
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dev->status_len = 9;
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dev->status_data[0] = dev->command | STATUS_LEN(9) | dev->cmd_dev;
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dev->status_data[1] = 0x0f03; /*Attention error, command not supported*/
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dev->status_data[2] = 0x0002; /*Interface fault*/
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dev->status_data[3] = 0;
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dev->status_data[4] = 0;
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dev->status_data[5] = 0;
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dev->status_data[6] = 0;
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dev->status_data[7] = 0;
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dev->status_data[8] = 0;
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dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_FAILURE;
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dev->irq_in_progress = 1;
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set_irq(dev);
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}
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static void
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device_not_present(esdi_t *dev)
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{
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dev->status_len = 9;
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dev->status_data[0] = dev->command | STATUS_LEN(9) | dev->cmd_dev;
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dev->status_data[1] = 0x0c11; /*Command failed, internal hardware error*/
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dev->status_data[2] = 0x000b; /*Selection error*/
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dev->status_data[3] = 0;
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dev->status_data[4] = 0;
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dev->status_data[5] = 0;
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dev->status_data[6] = 0;
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dev->status_data[7] = 0;
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dev->status_data[8] = 0;
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dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_FAILURE;
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dev->irq_in_progress = 1;
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set_irq(dev);
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}
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#define ESDI_ADAPTER_ONLY() do \
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{ \
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if (dev->cmd_dev != ATTN_HOST_ADAPTER) \
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{ \
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cmd_unsupported(dev); \
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return; \
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} \
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} while (0)
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#define ESDI_DRIVE_ONLY() do \
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{ \
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if (dev->cmd_dev != ATTN_DEVICE_0 && dev->cmd_dev != ATTN_DEVICE_1) \
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{ \
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cmd_unsupported(dev); \
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return; \
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} \
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if (dev->cmd_dev == ATTN_DEVICE_0) \
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drive = &dev->drives[0]; \
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else \
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drive = &dev->drives[1]; \
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} while (0)
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static void
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esdi_callback(void *priv)
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{
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esdi_t *dev = (esdi_t *)priv;
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drive_t *drive;
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int val;
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dev->callback = 0LL;
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/* If we are returning from a RESET, handle this first. */
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if (dev->in_reset) {
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dev->in_reset = 0;
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dev->status = STATUS_IRQ;
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dev->irq_status = IRQ_HOST_ADAPTER | IRQ_RESET_COMPLETE;
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return;
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}
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switch (dev->command) {
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case CMD_READ:
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ESDI_DRIVE_ONLY();
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if (! drive->present) {
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device_not_present(dev);
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return;
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}
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switch (dev->cmd_state) {
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case 0:
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dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
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dev->sector_pos = 0;
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dev->sector_count = dev->cmd_data[1];
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dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
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dev->irq_status = dev->cmd_dev | IRQ_DATA_TRANSFER_READY;
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dev->irq_in_progress = 1;
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set_irq(dev);
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dev->cmd_state = 1;
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dev->callback = ESDI_TIME;
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dev->data_pos = 0;
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break;
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case 1:
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if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
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dev->callback = ESDI_TIME;
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return;
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}
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while (dev->sector_pos < dev->sector_count) {
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if (! dev->data_pos) {
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if (dev->rba >= drive->sectors)
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fatal("Read past end of drive\n");
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hdd_image_read(drive->hdd_num, dev->rba, 1, (uint8_t *)dev->data);
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ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
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}
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while (dev->data_pos < 256) {
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val = dma_channel_write(dev->dma, dev->data[dev->data_pos]);
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if (val == DMA_NODATA) {
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dev->callback = ESDI_TIME;
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return;
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}
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dev->data_pos++;
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}
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dev->data_pos = 0;
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dev->sector_pos++;
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dev->rba++;
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}
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dev->status = STATUS_CMD_IN_PROGRESS;
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dev->cmd_state = 2;
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dev->callback = ESDI_TIME;
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break;
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case 2:
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dev->status = STATUS_IRQ;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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}
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break;
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case CMD_WRITE:
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case CMD_WRITE_VERIFY:
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ESDI_DRIVE_ONLY();
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if (! drive->present) {
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device_not_present(dev);
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return;
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}
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switch (dev->cmd_state) {
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case 0:
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dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
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dev->sector_pos = 0;
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dev->sector_count = dev->cmd_data[1];
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dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
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dev->irq_status = dev->cmd_dev | IRQ_DATA_TRANSFER_READY;
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dev->irq_in_progress = 1;
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set_irq(dev);
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dev->cmd_state = 1;
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dev->callback = ESDI_TIME;
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dev->data_pos = 0;
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break;
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case 1:
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if (! (dev->basic_ctrl & CTRL_DMA_ENA)) {
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dev->callback = ESDI_TIME;
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return;
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}
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while (dev->sector_pos < dev->sector_count) {
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while (dev->data_pos < 256) {
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val = dma_channel_read(dev->dma);
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if (val == DMA_NODATA) {
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dev->callback = ESDI_TIME;
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return;
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}
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dev->data[dev->data_pos++] = val & 0xffff;
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}
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if (dev->rba >= drive->sectors)
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fatal("Write past end of drive\n");
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hdd_image_write(drive->hdd_num, dev->rba, 1, (uint8_t *)dev->data);
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dev->rba++;
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dev->sector_pos++;
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ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
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dev->data_pos = 0;
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}
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ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
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dev->status = STATUS_CMD_IN_PROGRESS;
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dev->cmd_state = 2;
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dev->callback = ESDI_TIME;
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break;
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case 2:
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dev->status = STATUS_IRQ;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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}
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break;
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case CMD_READ_VERIFY:
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ESDI_DRIVE_ONLY();
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if (! drive->present) {
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device_not_present(dev);
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return;
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}
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dev->status = STATUS_IRQ;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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case CMD_SEEK:
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ESDI_DRIVE_ONLY();
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if (! drive->present) {
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device_not_present(dev);
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return;
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}
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dev->status = STATUS_IRQ;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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case CMD_GET_DEV_CONFIG:
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ESDI_DRIVE_ONLY();
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if (! drive->present) {
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device_not_present(dev);
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return;
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}
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if (dev->status_pos)
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fatal("Status send in progress\n");
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if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
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fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
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dev->status_len = 6;
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dev->status_data[0] = CMD_GET_POS_INFO | STATUS_LEN(6) | STATUS_DEVICE_HOST_ADAPTER;
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dev->status_data[1] = 0x10; /*Zero defect*/
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dev->status_data[2] = drive->sectors & 0xffff;
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dev->status_data[3] = drive->sectors >> 16;
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dev->status_data[4] = drive->tracks;
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dev->status_data[5] = drive->hpc | (drive->spt << 16);
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#if 0
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pclog("CMD_GET_DEV_CONFIG %i %04x %04x %04x %04x %04x %04x\n",
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drive->sectors,
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dev->status_data[0], dev->status_data[1],
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dev->status_data[2], dev->status_data[3],
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dev->status_data[4], dev->status_data[5]);
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#endif
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dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
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dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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case CMD_GET_POS_INFO:
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ESDI_ADAPTER_ONLY();
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if (dev->status_pos)
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fatal("Status send in progress\n");
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if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
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fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
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dev->status_len = 5;
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dev->status_data[0] = CMD_GET_POS_INFO | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER;
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dev->status_data[1] = 0xffdd; /*MCA ID*/
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dev->status_data[2] = dev->pos_regs[3] |
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(dev->pos_regs[2] << 8);
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dev->status_data[3] = 0xffff;
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dev->status_data[4] = 0xffff;
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dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
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dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
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dev->irq_in_progress = 1;
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set_irq(dev);
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break;
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|
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case 0x10:
|
|
ESDI_ADAPTER_ONLY();
|
|
switch (dev->cmd_state) {
|
|
case 0:
|
|
dev->sector_pos = 0;
|
|
dev->sector_count = dev->cmd_data[1];
|
|
if (dev->sector_count > 256)
|
|
fatal("Write sector buffer count %04x\n", dev->cmd_data[1]);
|
|
|
|
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
|
|
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY;
|
|
dev->irq_in_progress = 1;
|
|
set_irq(dev);
|
|
|
|
dev->cmd_state = 1;
|
|
dev->callback = ESDI_TIME;
|
|
dev->data_pos = 0;
|
|
break;
|
|
|
|
case 1:
|
|
if (! (dev->basic_ctrl & CTRL_DMA_ENA)) {
|
|
dev->callback = ESDI_TIME;
|
|
return;
|
|
}
|
|
while (dev->sector_pos < dev->sector_count) {
|
|
while (dev->data_pos < 256) {
|
|
val = dma_channel_read(dev->dma);
|
|
|
|
if (val == DMA_NODATA) {
|
|
dev->callback = ESDI_TIME;
|
|
return;
|
|
}
|
|
|
|
dev->data[dev->data_pos++] = val & 0xffff;;
|
|
}
|
|
|
|
memcpy(dev->sector_buffer[dev->sector_pos++], dev->data, 512);
|
|
dev->data_pos = 0;
|
|
}
|
|
|
|
dev->status = STATUS_CMD_IN_PROGRESS;
|
|
dev->cmd_state = 2;
|
|
dev->callback = ESDI_TIME;
|
|
break;
|
|
|
|
case 2:
|
|
dev->status = STATUS_IRQ;
|
|
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
|
|
dev->irq_in_progress = 1;
|
|
set_irq(dev);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 0x11:
|
|
ESDI_ADAPTER_ONLY();
|
|
switch (dev->cmd_state) {
|
|
case 0:
|
|
dev->sector_pos = 0;
|
|
dev->sector_count = dev->cmd_data[1];
|
|
if (dev->sector_count > 256)
|
|
fatal("Read sector buffer count %04x\n", dev->cmd_data[1]);
|
|
|
|
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
|
|
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY;
|
|
dev->irq_in_progress = 1;
|
|
set_irq(dev);
|
|
|
|
dev->cmd_state = 1;
|
|
dev->callback = ESDI_TIME;
|
|
dev->data_pos = 0;
|
|
break;
|
|
|
|
case 1:
|
|
if (! (dev->basic_ctrl & CTRL_DMA_ENA)) {
|
|
dev->callback = ESDI_TIME;
|
|
return;
|
|
}
|
|
|
|
while (dev->sector_pos < dev->sector_count) {
|
|
if (! dev->data_pos)
|
|
memcpy(dev->data, dev->sector_buffer[dev->sector_pos++], 512);
|
|
while (dev->data_pos < 256) {
|
|
val = dma_channel_write(dev->dma, dev->data[dev->data_pos]);
|
|
|
|
if (val == DMA_NODATA) {
|
|
dev->callback = ESDI_TIME;
|
|
return;
|
|
}
|
|
|
|
dev->data_pos++;
|
|
}
|
|
|
|
dev->data_pos = 0;
|
|
}
|
|
|
|
dev->status = STATUS_CMD_IN_PROGRESS;
|
|
dev->cmd_state = 2;
|
|
dev->callback = ESDI_TIME;
|
|
break;
|
|
|
|
case 2:
|
|
dev->status = STATUS_IRQ;
|
|
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
|
|
dev->irq_in_progress = 1;
|
|
set_irq(dev);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 0x12:
|
|
ESDI_ADAPTER_ONLY();
|
|
if (dev->status_pos)
|
|
fatal("Status send in progress\n");
|
|
if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
|
|
fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
|
|
|
|
dev->status_len = 2;
|
|
dev->status_data[0] = 0x12 | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER;
|
|
dev->status_data[1] = 0;
|
|
|
|
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
|
|
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
|
|
dev->irq_in_progress = 1;
|
|
set_irq(dev);
|
|
break;
|
|
|
|
default:
|
|
fatal("BAD COMMAND %02x %i\n", dev->command, dev->cmd_dev);
|
|
}
|
|
}
|
|
|
|
|
|
static uint8_t
|
|
esdi_read(uint16_t port, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
uint8_t ret = 0xff;
|
|
|
|
switch (port-dev->base) {
|
|
case 2: /*Basic status register*/
|
|
ret = dev->status;
|
|
break;
|
|
|
|
case 3: /*IRQ status*/
|
|
dev->status &= ~STATUS_IRQ;
|
|
ret = dev->irq_status;
|
|
break;
|
|
|
|
default:
|
|
fatal("esdi_read port=%04x\n", port);
|
|
}
|
|
|
|
return(ret);
|
|
}
|
|
|
|
|
|
static void
|
|
esdi_write(uint16_t port, uint8_t val, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
|
|
#if 0
|
|
pclog("ESDI: wr(%04x, %02x)\n", port-dev->base, val);
|
|
#endif
|
|
switch (port-dev->base) {
|
|
case 2: /*Basic control register*/
|
|
if ((dev->basic_ctrl & CTRL_RESET) && !(val & CTRL_RESET)) {
|
|
dev->in_reset = 1;
|
|
dev->callback = ESDI_TIME * 50LL;
|
|
dev->status = STATUS_BUSY;
|
|
}
|
|
dev->basic_ctrl = val;
|
|
|
|
if (! (dev->basic_ctrl & CTRL_IRQ_ENA))
|
|
picintc(1 << dev->irq);
|
|
break;
|
|
|
|
case 3: /*Attention register*/
|
|
switch (val & ATTN_DEVICE_SEL) {
|
|
case ATTN_HOST_ADAPTER:
|
|
switch (val & ATTN_REQ_MASK) {
|
|
case ATTN_CMD_REQ:
|
|
if (dev->cmd_req_in_progress)
|
|
fatal("Try to start command on in_progress adapter\n");
|
|
dev->cmd_req_in_progress = 1;
|
|
dev->cmd_dev = ATTN_HOST_ADAPTER;
|
|
dev->status |= STATUS_BUSY;
|
|
dev->cmd_pos = 0;
|
|
break;
|
|
|
|
case ATTN_EOI:
|
|
dev->irq_in_progress = 0;
|
|
dev->status &= ~STATUS_IRQ;
|
|
clear_irq(dev);
|
|
break;
|
|
|
|
case ATTN_RESET:
|
|
dev->in_reset = 1;
|
|
dev->callback = ESDI_TIME * 50LL;
|
|
dev->status = STATUS_BUSY;
|
|
break;
|
|
|
|
default:
|
|
fatal("Bad attention request %02x\n", val);
|
|
}
|
|
break;
|
|
|
|
case ATTN_DEVICE_0:
|
|
switch (val & ATTN_REQ_MASK) {
|
|
case ATTN_CMD_REQ:
|
|
if (dev->cmd_req_in_progress)
|
|
fatal("Try to start command on in_progress device0\n");
|
|
dev->cmd_req_in_progress = 1;
|
|
dev->cmd_dev = ATTN_DEVICE_0;
|
|
dev->status |= STATUS_BUSY;
|
|
dev->cmd_pos = 0;
|
|
break;
|
|
|
|
case ATTN_EOI:
|
|
dev->irq_in_progress = 0;
|
|
dev->status &= ~STATUS_IRQ;
|
|
clear_irq(dev);
|
|
break;
|
|
|
|
default:
|
|
fatal("Bad attention request %02x\n", val);
|
|
}
|
|
break;
|
|
|
|
case ATTN_DEVICE_1:
|
|
switch (val & ATTN_REQ_MASK) {
|
|
case ATTN_CMD_REQ:
|
|
if (dev->cmd_req_in_progress)
|
|
fatal("Try to start command on in_progress device0\n");
|
|
dev->cmd_req_in_progress = 1;
|
|
dev->cmd_dev = ATTN_DEVICE_1;
|
|
dev->status |= STATUS_BUSY;
|
|
dev->cmd_pos = 0;
|
|
break;
|
|
|
|
case ATTN_EOI:
|
|
dev->irq_in_progress = 0;
|
|
dev->status &= ~STATUS_IRQ;
|
|
clear_irq(dev);
|
|
break;
|
|
|
|
default:
|
|
fatal("Bad attention request %02x\n", val);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fatal("Attention to unknown device %02x\n", val);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fatal("esdi_write port=%04x val=%02x\n", port, val);
|
|
}
|
|
}
|
|
|
|
|
|
static uint16_t
|
|
esdi_readw(uint16_t port, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
uint16_t ret = 0xffff;
|
|
|
|
switch (port-dev->base) {
|
|
case 0: /*Status Interface Register*/
|
|
if (dev->status_pos >= dev->status_len)
|
|
return(0);
|
|
ret = dev->status_data[dev->status_pos++];
|
|
if (dev->status_pos >= dev->status_len) {
|
|
dev->status &= ~STATUS_STATUS_OUT_FULL;
|
|
dev->status_pos = dev->status_len = 0;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fatal("esdi_readw port=%04x\n", port);
|
|
}
|
|
|
|
return(ret);
|
|
}
|
|
|
|
|
|
static void
|
|
esdi_writew(uint16_t port, uint16_t val, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
|
|
#if 0
|
|
pclog("ESDI: wrw(%04x, %04x)\n", port-dev->base, val);
|
|
#endif
|
|
switch (port-dev->base) {
|
|
case 0: /*Command Interface Register*/
|
|
if (dev->cmd_pos >= 4)
|
|
fatal("CIR pos 4\n");
|
|
dev->cmd_data[dev->cmd_pos++] = val;
|
|
if (((dev->cmd_data[0] & CMD_SIZE_4) && dev->cmd_pos == 4) ||
|
|
(!(dev->cmd_data[0] & CMD_SIZE_4) && dev->cmd_pos == 2)) {
|
|
dev->cmd_pos = 0;
|
|
dev->cmd_req_in_progress = 0;
|
|
dev->cmd_state = 0;
|
|
|
|
if ((dev->cmd_data[0] & CMD_DEVICE_SEL) != dev->cmd_dev)
|
|
fatal("Command device mismatch with attn\n");
|
|
dev->command = dev->cmd_data[0] & CMD_MASK;
|
|
dev->callback = ESDI_TIME;
|
|
dev->status = STATUS_BUSY;
|
|
dev->data_pos = 0;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fatal("esdi_writew port=%04x val=%04x\n", port, val);
|
|
}
|
|
}
|
|
|
|
|
|
static uint8_t
|
|
esdi_mca_read(int port, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
|
|
#if 0
|
|
pclog("ESDI: mcard(%04x)\n", port);
|
|
#endif
|
|
return(dev->pos_regs[port & 7]);
|
|
}
|
|
|
|
|
|
static void
|
|
esdi_mca_write(int port, uint8_t val, void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
|
|
#if 0
|
|
pclog("ESDI: mcawr(%04x, %02x) pos[2]=%02x pos[3]=%02x\n",
|
|
port, val, dev->pos_regs[2], dev->pos_regs[3]);
|
|
#endif
|
|
if (port < 0x102) return;
|
|
|
|
/* Save the new value. */
|
|
dev->pos_regs[port & 7] = val;
|
|
|
|
/* Extract the new I/O base. */
|
|
switch(dev->pos_regs[2] & 0x02) {
|
|
case 0x00: /* PRIMARY [0]=XXxx xx0X 0x3510 */
|
|
dev->base = ESDI_IOADDR_PRI;
|
|
break;
|
|
|
|
case 0x02: /* SECONDARY [0]=XXxx xx1X 0x3518 */
|
|
dev->base = ESDI_IOADDR_SEC;
|
|
break;
|
|
}
|
|
|
|
/* Extract the new DMA channel. */
|
|
switch(dev->pos_regs[2] & 0x3c) {
|
|
case 0x14: /* DMA 5 [0]=XX01 01XX */
|
|
dev->dma = 5;
|
|
break;
|
|
|
|
case 0x18: /* DMA 6 [0]=XX01 10XX */
|
|
dev->dma = 6;
|
|
break;
|
|
|
|
case 0x1c: /* DMA 7 [0]=XX01 11XX */
|
|
dev->dma = 7;
|
|
break;
|
|
|
|
case 0x00: /* DMA 0 [0]=XX00 00XX */
|
|
dev->dma = 0;
|
|
break;
|
|
|
|
case 0x01: /* DMA 1 [0]=XX00 01XX */
|
|
dev->dma = 1;
|
|
break;
|
|
|
|
case 0x04: /* DMA 3 [0]=XX00 11XX */
|
|
dev->dma = 3;
|
|
break;
|
|
|
|
case 0x10: /* DMA 4 [0]=XX01 00XX */
|
|
dev->dma = 4;
|
|
break;
|
|
}
|
|
|
|
/* Extract the new BIOS address. */
|
|
if (! (dev->pos_regs[3] & 0x08)) switch(dev->pos_regs[3] & 0x0f) {
|
|
case 0: /* ROM C000 [1]=XXXX 0000 */
|
|
dev->bios = 0xC0000;
|
|
break;
|
|
|
|
case 1: /* ROM C400 [1]=XXXX 0001 */
|
|
dev->bios = 0xC4000;
|
|
break;
|
|
|
|
case 2: /* ROM C800 [1]=XXXX 0010 */
|
|
dev->bios = 0xC8000;
|
|
break;
|
|
|
|
case 3: /* ROM CC00 [1]=XXXX 0011 */
|
|
dev->bios = 0xCC000;
|
|
break;
|
|
|
|
case 4: /* ROM D000 [1]=XXXX 0100 */
|
|
dev->bios = 0xD0000;
|
|
break;
|
|
|
|
case 5: /* ROM D400 [1]=XXXX 0101 */
|
|
dev->bios = 0xD4000;
|
|
break;
|
|
|
|
case 6: /* ROM D800 [1]=XXXX 0110 */
|
|
dev->bios = 0xD8000;
|
|
break;
|
|
|
|
case 7: /* ROM DC00 [1]=XXXX 0111 */
|
|
dev->bios = 0xC0000;
|
|
break;
|
|
} else {
|
|
/* BIOS ROM disabled. */
|
|
dev->bios = 0x000000;
|
|
}
|
|
|
|
/*
|
|
* The PS/2 Model 80 BIOS always enables a card if it finds one,
|
|
* even if no resources were assigned yet (because we only added
|
|
* the card, but have not run AutoConfig yet...)
|
|
*
|
|
* So, remove current address, if any.
|
|
*/
|
|
io_removehandler(dev->base, 8,
|
|
esdi_read, esdi_readw, NULL,
|
|
esdi_write, esdi_writew, NULL, dev);
|
|
mem_mapping_disable(&dev->bios_rom.mapping);
|
|
|
|
if (dev->pos_regs[2] & 0x01) {
|
|
/* Card enabled; register (new) I/O handler. */
|
|
io_sethandler(dev->base, 8,
|
|
esdi_read, esdi_readw, NULL,
|
|
esdi_write, esdi_writew, NULL, dev);
|
|
|
|
/* Enable or disable the BIOS ROM. */
|
|
if (dev->bios != 0x000000) {
|
|
mem_mapping_enable(&dev->bios_rom.mapping);
|
|
mem_mapping_set_addr(&dev->bios_rom.mapping,
|
|
dev->bios, 0x4000);
|
|
}
|
|
|
|
/* Say hello. */
|
|
pclog("ESDI: I/O=%04x, IRQ=%d, DMA=%d, BIOS @%05X\n",
|
|
dev->base, dev->irq, dev->dma, dev->bios);
|
|
}
|
|
}
|
|
|
|
|
|
static void *
|
|
esdi_init(device_t *info)
|
|
{
|
|
drive_t *drive;
|
|
esdi_t *dev;
|
|
int c, i;
|
|
|
|
dev = malloc(sizeof(esdi_t));
|
|
if (dev == NULL) return(NULL);
|
|
memset(dev, 0x00, sizeof(esdi_t));
|
|
|
|
/* Mark as unconfigured. */
|
|
dev->irq_status = 0xff;
|
|
|
|
/* This is hardwired. */
|
|
dev->irq = ESDI_IRQCHAN;
|
|
|
|
rom_init_interleaved(&dev->bios_rom,
|
|
BIOS_FILE_L, BIOS_FILE_H,
|
|
0x00000, 16384, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
|
|
mem_mapping_disable(&dev->bios_rom.mapping);
|
|
|
|
dev->drives[0].present = dev->drives[1].present = 0;
|
|
|
|
for (c=0,i=0; i<HDD_NUM; i++) {
|
|
if ((hdd[i].bus == HDD_BUS_ESDI) && (hdd[i].esdi_channel < ESDI_NUM)) {
|
|
/* This is an ESDI drive. */
|
|
drive = &dev->drives[hdd[i].esdi_channel];
|
|
|
|
/* Try to load an image for the drive. */
|
|
if (! hdd_image_load(i)) {
|
|
/* Nope. */
|
|
drive->present = 0;
|
|
continue;
|
|
}
|
|
|
|
/* OK, so fill in geometry info. */
|
|
drive->spt = hdd[i].spt;
|
|
drive->hpc = hdd[i].hpc;
|
|
drive->tracks = hdd[i].tracks;
|
|
drive->sectors = hdd[i].spt*hdd[i].hpc*hdd[i].tracks;
|
|
drive->hdd_num = i;
|
|
|
|
/* Mark drive as present. */
|
|
drive->present = 1;
|
|
}
|
|
|
|
if (++c >= ESDI_NUM) break;
|
|
}
|
|
|
|
/* Set the MCA ID for this controller, 0xFFDD. */
|
|
dev->pos_regs[0] = 0xff;
|
|
dev->pos_regs[1] = 0xdd;
|
|
|
|
/* Enable the device. */
|
|
mca_add(esdi_mca_read, esdi_mca_write, dev);
|
|
|
|
/* Mark for a reset. */
|
|
dev->in_reset = 1;
|
|
dev->callback = ESDI_TIME * 50LL;
|
|
dev->status = STATUS_BUSY;
|
|
|
|
/* Set the reply timer. */
|
|
timer_add(esdi_callback, &dev->callback, &dev->callback, dev);
|
|
|
|
return(dev);
|
|
}
|
|
|
|
|
|
static void
|
|
esdi_close(void *priv)
|
|
{
|
|
esdi_t *dev = (esdi_t *)priv;
|
|
drive_t *drive;
|
|
int d;
|
|
|
|
dev->drives[0].present = dev->drives[1].present = 0;
|
|
|
|
for (d=0; d<2; d++) {
|
|
drive = &dev->drives[d];
|
|
|
|
hdd_image_close(drive->hdd_num);
|
|
}
|
|
|
|
free(dev);
|
|
}
|
|
|
|
|
|
static int
|
|
esdi_available(void)
|
|
{
|
|
return(rom_present(BIOS_FILE_L) && rom_present(BIOS_FILE_H));
|
|
}
|
|
|
|
|
|
device_t esdi_ps2_device = {
|
|
"IBM ESDI Fixed Disk Adapter (MCA)",
|
|
DEVICE_MCA, 0,
|
|
esdi_init, esdi_close, NULL,
|
|
esdi_available, NULL, NULL, NULL, NULL
|
|
};
|