7c67e867c8
IBM.H is gone, video stuff re-organized. Keyboard stuff reorganized. Machines that have their own video, mouse and/or keyboard now have all this in their machine file. Fixed and other cleanups here and there.
1139 lines
28 KiB
C
1139 lines
28 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the AHA-154x series of SCSI Host Adapters
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* made by Adaptec, Inc. These controllers were designed for
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* the ISA bus.
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*
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* Version: @(#)scsi_aha154x.c 1.0.34 2017/11/04
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*
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* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
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* Original Buslogic version by SA1988 and Miran Grca.
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*
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* Copyright 2017 Fred N. van Kempen.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../io.h"
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#include "../mca.h"
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#include "../mem.h"
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#include "../mca.h"
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#include "../rom.h"
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#include "../nvr.h"
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#include "../dma.h"
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#include "../pic.h"
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#include "../timer.h"
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#include "../device.h"
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#include "../plat.h"
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#include "scsi.h"
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#include "scsi_aha154x.h"
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#include "scsi_x54x.h"
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enum {
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AHA_154xB,
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AHA_154xC,
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AHA_154xCF,
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AHA_154xCP,
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AHA_1640
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};
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#define CMD_WRITE_EEPROM 0x22 /* UNDOC: Write EEPROM */
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#define CMD_READ_EEPROM 0x23 /* UNDOC: Read EEPROM */
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#define CMD_SHADOW_RAM 0x24 /* UNDOC: BIOS shadow ram */
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#define CMD_BIOS_MBINIT 0x25 /* UNDOC: BIOS mailbox initialization */
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#define CMD_MEMORY_MAP_1 0x26 /* UNDOC: Memory Mapper */
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#define CMD_MEMORY_MAP_2 0x27 /* UNDOC: Memory Mapper */
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#define CMD_EXTBIOS 0x28 /* UNDOC: return extended BIOS info */
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#define CMD_MBENABLE 0x29 /* set mailbox interface enable */
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#define CMD_BIOS_SCSI 0x82 /* start ROM BIOS SCSI command */
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uint16_t aha_ports[] = {
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0x0330, 0x0334, 0x0230, 0x0234,
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0x0130, 0x0134, 0x0000, 0x0000
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};
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#pragma pack(push,1)
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typedef struct {
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uint8_t CustomerSignature[20];
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uint8_t uAutoRetry;
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uint8_t uBoardSwitches;
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uint8_t uChecksum;
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uint8_t uUnknown;
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addr24 BIOSMailboxAddress;
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} aha_setup_t;
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#pragma pack(pop)
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#ifdef ENABLE_AHA154X_LOG
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int aha_do_log = ENABLE_AHA154X_LOG;
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#endif
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static void
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aha_log(const char *fmt, ...)
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{
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#ifdef ENABLE_AHA154X_LOG
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va_list ap;
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if (aha_do_log) {
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va_start(ap, fmt);
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vprintf(fmt, ap);
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va_end(ap);
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fflush(stdout);
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}
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#endif
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}
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/*
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* Write data to the BIOS space.
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*
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* AHA-1542C's and up have a feature where they map a 128-byte
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* RAM space into the ROM BIOS' address space, and then use it
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* as working memory. This function implements the writing to
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* that memory.
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*
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* We enable/disable this memory through AHA command 0x24.
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*/
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static void
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aha_mem_write(uint32_t addr, uint8_t val, void *priv)
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{
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x54x_t *dev = (x54x_t *)priv;
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addr &= 0x3fff;
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if ((addr >= dev->rom_shram) && (dev->shram_mode & 1))
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dev->shadow_ram[addr & (dev->rom_shramsz - 1)] = val;
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}
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static uint8_t
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aha_mem_read(uint32_t addr, void *priv)
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{
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x54x_t *dev = (x54x_t *)priv;
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rom_t *rom = &dev->bios;
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addr &= 0x3fff;
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if ((addr >= dev->rom_shram) && (dev->shram_mode & 2))
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return dev->shadow_ram[addr & (dev->rom_shramsz - 1)];
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return(rom->rom[addr]);
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}
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static uint8_t
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aha154x_shram(x54x_t *dev, uint8_t cmd)
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{
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/* If not supported, give up. */
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if (dev->rom_shram == 0x0000) return(0x04);
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/* Bit 0 = Shadow RAM write enable;
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Bit 1 = Shadow RAM read enable. */
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dev->shram_mode = cmd;
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/* Firmware expects 04 status. */
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return(0x04);
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}
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static void
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aha_eeprom_save(x54x_t *dev)
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{
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FILE *f;
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f = nvr_fopen(dev->nvr_path, L"wb");
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if (f)
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{
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fwrite(dev->nvr, 1, NVR_SIZE, f);
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fclose(f);
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f = NULL;
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}
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}
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static uint8_t
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aha154x_eeprom(x54x_t *dev, uint8_t cmd,uint8_t arg,uint8_t len,uint8_t off,uint8_t *bufp)
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{
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uint8_t r = 0xff;
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int c;
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aha_log("%s: EEPROM cmd=%02x, arg=%02x len=%d, off=%02x\n",
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dev->name, cmd, arg, len, off);
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/* Only if we can handle it.. */
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if (dev->nvr == NULL) return(r);
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if (cmd == 0x22) {
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/* Write data to the EEPROM. */
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for (c = 0; c < len; c++)
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dev->nvr[(off + c) & 0xff] = bufp[c];
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r = 0;
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aha_eeprom_save(dev);
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}
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if (cmd == 0x23) {
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/* Read data from the EEPROM. */
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for (c = 0; c < len; c++)
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bufp[c] = dev->nvr[(off + c) & 0xff];
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r = len;
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}
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return(r);
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}
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/* Map either the main or utility (Select) ROM into the memory space. */
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static uint8_t
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aha154x_mmap(x54x_t *dev, uint8_t cmd)
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{
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aha_log("%s: MEMORY cmd=%02x\n", dev->name, cmd);
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switch(cmd) {
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case 0x26:
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/* Disable the mapper, so, set ROM1 active. */
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dev->bios.rom = dev->rom1;
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break;
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case 0x27:
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/* Enable the mapper, so, set ROM2 active. */
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dev->bios.rom = dev->rom2;
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break;
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}
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return(0);
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}
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static uint8_t
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aha_get_host_id(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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return dev->nvr[0] & 0x07;
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}
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static uint8_t
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aha_get_irq(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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return (dev->nvr[1] & 0x07) + 9;
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}
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static uint8_t
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aha_get_dma(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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return (dev->nvr[1] >> 4) & 0x07;
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}
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static uint8_t
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aha_cmd_is_fast(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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if (dev->Command == CMD_BIOS_SCSI)
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return 1;
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else
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return 0;
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}
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static uint8_t
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aha_fast_cmds(void *p, uint8_t cmd)
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{
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x54x_t *dev = (x54x_t *)p;
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if (cmd == CMD_BIOS_SCSI) {
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x54x_busy(1);
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dev->BIOSMailboxReq++;
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x54x_set_wait_event();
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x54x_busy(0);
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return 1;
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}
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return 0;
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}
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static uint8_t
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aha_param_len(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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switch (dev->Command) {
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case CMD_BIOS_MBINIT:
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/* Same as 0x01 for AHA. */
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return sizeof(MailboxInit_t);
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break;
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case CMD_SHADOW_RAM:
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return 1;
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break;
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case CMD_WRITE_EEPROM:
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return 3+32;
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break;
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case CMD_READ_EEPROM:
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return 3;
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case CMD_MBENABLE:
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return 2;
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default:
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return 0;
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}
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}
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static uint8_t
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aha_cmds(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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MailboxInit_t *mbi;
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if (! dev->CmdParamLeft) {
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aha_log("Running Operation Code 0x%02X\n", dev->Command);
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switch (dev->Command) {
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case CMD_WRITE_EEPROM: /* write EEPROM */
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/* Sent by CF BIOS. */
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dev->DataReplyLeft =
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aha154x_eeprom(dev,
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dev->Command,
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dev->CmdBuf[0],
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dev->CmdBuf[1],
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dev->CmdBuf[2],
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&(dev->CmdBuf[3]));
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if (dev->DataReplyLeft == 0xff) {
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dev->DataReplyLeft = 0;
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dev->Status |= STAT_INVCMD;
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}
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break;
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case CMD_READ_EEPROM: /* read EEPROM */
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/* Sent by CF BIOS. */
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dev->DataReplyLeft =
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aha154x_eeprom(dev,
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dev->Command,
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dev->CmdBuf[0],
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dev->CmdBuf[1],
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dev->CmdBuf[2],
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dev->DataBuf);
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if (dev->DataReplyLeft == 0xff) {
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dev->DataReplyLeft = 0;
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dev->Status |= STAT_INVCMD;
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}
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break;
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case CMD_SHADOW_RAM: /* Shadow RAM */
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/*
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* For AHA1542CF, this is the command
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* to play with the Shadow RAM. BIOS
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* gives us one argument (00,02,03)
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* and expects a 0x04 back in the INTR
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* register. --FvK
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*/
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/* dev->Interrupt = aha154x_shram(dev,val); */
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dev->Interrupt = aha154x_shram(dev, dev->CmdBuf[0]);
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break;
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case CMD_BIOS_MBINIT: /* BIOS Mailbox Initialization */
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/* Sent by CF BIOS. */
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x54x_busy(1);
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dev->Mbx24bit = 1;
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mbi = (MailboxInit_t *)dev->CmdBuf;
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dev->BIOSMailboxInit = 1;
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dev->BIOSMailboxCount = mbi->Count;
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dev->BIOSMailboxOutAddr = ADDR_TO_U32(mbi->Address);
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aha_log("Initialize BIOS Mailbox: MBO=0x%08lx, %d entries at 0x%08lx\n",
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dev->BIOSMailboxOutAddr,
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mbi->Count,
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ADDR_TO_U32(mbi->Address));
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dev->Status &= ~STAT_INIT;
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dev->DataReplyLeft = 0;
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x54x_busy(0);
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break;
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case CMD_MEMORY_MAP_1: /* AHA memory mapper */
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case CMD_MEMORY_MAP_2: /* AHA memory mapper */
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/* Sent by CF BIOS. */
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dev->DataReplyLeft =
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aha154x_mmap(dev, dev->Command);
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break;
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case CMD_EXTBIOS: /* Return extended BIOS information */
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dev->DataBuf[0] = 0x08;
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dev->DataBuf[1] = dev->Lock;
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dev->DataReplyLeft = 2;
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break;
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case CMD_MBENABLE: /* Mailbox interface enable Command */
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dev->DataReplyLeft = 0;
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if (dev->CmdBuf[1] == dev->Lock) {
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if (dev->CmdBuf[0] & 1) {
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dev->Lock = 1;
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} else {
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dev->Lock = 0;
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}
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}
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break;
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case 0x2C: /* AHA-1542CP sends this */
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dev->DataBuf[0] = 0x00;
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dev->DataReplyLeft = 1;
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break;
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case 0x33: /* AHA-1542CP sends this */
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dev->DataBuf[0] = 0x00;
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dev->DataBuf[1] = 0x00;
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dev->DataBuf[2] = 0x00;
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dev->DataBuf[3] = 0x00;
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dev->DataReplyLeft = 256;
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break;
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default:
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dev->DataReplyLeft = 0;
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dev->Status |= STAT_INVCMD;
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break;
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}
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}
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return 0;
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}
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static void
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aha_setup_data(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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ReplyInquireSetupInformation *ReplyISI;
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aha_setup_t *aha_setup;
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ReplyISI = (ReplyInquireSetupInformation *)dev->DataBuf;
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aha_setup = (aha_setup_t *)ReplyISI->VendorSpecificData;
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ReplyISI->fSynchronousInitiationEnabled = dev->sync & 1;
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ReplyISI->fParityCheckingEnabled = dev->parity & 1;
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U32_TO_ADDR(aha_setup->BIOSMailboxAddress, dev->BIOSMailboxOutAddr);
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aha_setup->uChecksum = 0xA3;
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aha_setup->uUnknown = 0xC2;
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}
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static void
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aha_do_bios_mail(x54x_t *dev)
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{
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dev->MailboxIsBIOS = 1;
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if (!dev->BIOSMailboxCount) {
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aha_log("aha_do_bios_mail(): No BIOS Mailboxes\n");
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return;
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}
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/* Search for a filled mailbox - stop if we have scanned all mailboxes. */
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for (dev->BIOSMailboxOutPosCur = 0; dev->BIOSMailboxOutPosCur < dev->BIOSMailboxCount; dev->BIOSMailboxOutPosCur++) {
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if (x54x_mbo_process(dev))
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break;
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}
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}
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static void
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aha_thread(void *p)
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{
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x54x_t *dev = (x54x_t *)p;
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if (dev->BIOSMailboxInit && dev->BIOSMailboxReq)
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{
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x54x_wait_for_poll();
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aha_do_bios_mail(dev);
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}
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}
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static uint8_t
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aha_mca_read(int port, void *priv)
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{
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x54x_t *dev = (x54x_t *)priv;
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return(dev->pos_regs[port & 7]);
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}
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static void
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aha_mca_write(int port, uint8_t val, void *priv)
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{
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x54x_t *dev = (x54x_t *)priv;
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/* MCA does not write registers below 0x0100. */
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if (port < 0x0102) return;
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/* Save the MCA register value. */
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dev->pos_regs[port & 7] = val;
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/* This is always necessary so that the old handler doesn't remain. */
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x54x_io_remove(dev, dev->Base, 4);
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/* Get the new assigned I/O base address. */
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dev->Base = (dev->pos_regs[3] & 7) << 8;
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dev->Base |= ((dev->pos_regs[3] & 0xc0) ? 4 : 0);
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/* Save the new IRQ and DMA channel values. */
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dev->Irq = (dev->pos_regs[4] & 0x07) + 8;
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dev->DmaChannel = dev->pos_regs[5] & 0x0f;
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/* Extract the BIOS ROM address info. */
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if (! (dev->pos_regs[2] & 0x80)) switch(dev->pos_regs[3] & 0x38) {
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case 0x38: /* [1]=xx11 1xxx */
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dev->rom_addr = 0xDC000;
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break;
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case 0x30: /* [1]=xx11 0xxx */
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dev->rom_addr = 0xD8000;
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break;
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case 0x28: /* [1]=xx10 1xxx */
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dev->rom_addr = 0xD4000;
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break;
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case 0x20: /* [1]=xx10 0xxx */
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dev->rom_addr = 0xD0000;
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break;
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case 0x18: /* [1]=xx01 1xxx */
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dev->rom_addr = 0xCC000;
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break;
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case 0x10: /* [1]=xx01 0xxx */
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dev->rom_addr = 0xC8000;
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break;
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} else {
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/* Disabled. */
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dev->rom_addr = 0x000000;
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}
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|
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/*
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* Get misc SCSI config stuff. For now, we are only
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* interested in the configured HA target ID:
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*
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* pos[2]=111xxxxx = 7
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* pos[2]=000xxxxx = 0
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*/
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dev->HostID = (dev->pos_regs[4] >> 5) & 0x07;
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|
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/*
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* SYNC mode is pos[2]=xxxx1xxx.
|
|
*
|
|
* SCSI Parity is pos[2]=xxx1xxxx.
|
|
*/
|
|
dev->sync = (dev->pos_regs[4] >> 3) & 1;
|
|
dev->parity = (dev->pos_regs[4] >> 4) & 1;
|
|
|
|
/*
|
|
* The PS/2 Model 80 BIOS always enables a card if it finds one,
|
|
* even if no resources were assigned yet (because we only added
|
|
* the card, but have not run AutoConfig yet...)
|
|
*
|
|
* So, remove current address, if any.
|
|
*/
|
|
mem_mapping_disable(&dev->bios.mapping);
|
|
|
|
/* Initialize the device if fully configured. */
|
|
if (dev->pos_regs[2] & 0x01) {
|
|
/* Card enabled; register (new) I/O handler. */
|
|
x54x_io_set(dev, dev->Base, 4);
|
|
|
|
/* Reset the device. */
|
|
x54x_reset_ctrl(dev, CTRL_HRST);
|
|
|
|
/* Enable or disable the BIOS ROM. */
|
|
if (dev->rom_addr != 0x000000) {
|
|
mem_mapping_enable(&dev->bios.mapping);
|
|
mem_mapping_set_addr(&dev->bios.mapping, dev->rom_addr, ROM_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* Initialize the board's ROM BIOS. */
|
|
static void
|
|
aha_setbios(x54x_t *dev)
|
|
{
|
|
uint32_t size;
|
|
uint32_t mask;
|
|
uint32_t temp;
|
|
FILE *f;
|
|
int i;
|
|
|
|
/* Only if this device has a BIOS ROM. */
|
|
if (dev->bios_path == NULL) return;
|
|
|
|
/* Open the BIOS image file and make sure it exists. */
|
|
aha_log("%s: loading BIOS from '%ls'\n", dev->name, dev->bios_path);
|
|
if ((f = rom_fopen(dev->bios_path, L"rb")) == NULL) {
|
|
aha_log("%s: BIOS ROM not found!\n", dev->name);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Manually load and process the ROM image.
|
|
*
|
|
* We *could* use the system "rom_init" function here, but for
|
|
* this special case, we can't: we may need WRITE access to the
|
|
* memory later on.
|
|
*/
|
|
(void)fseek(f, 0L, SEEK_END);
|
|
temp = ftell(f);
|
|
(void)fseek(f, 0L, SEEK_SET);
|
|
|
|
/* Load first chunk of BIOS (which is the main BIOS, aka ROM1.) */
|
|
dev->rom1 = malloc(ROM_SIZE);
|
|
(void)fread(dev->rom1, ROM_SIZE, 1, f);
|
|
temp -= ROM_SIZE;
|
|
if (temp > 0) {
|
|
dev->rom2 = malloc(ROM_SIZE);
|
|
(void)fread(dev->rom2, ROM_SIZE, 1, f);
|
|
temp -= ROM_SIZE;
|
|
} else {
|
|
dev->rom2 = NULL;
|
|
}
|
|
if (temp != 0) {
|
|
aha_log("%s: BIOS ROM size invalid!\n", dev->name);
|
|
free(dev->rom1);
|
|
if (dev->rom2 != NULL)
|
|
free(dev->rom2);
|
|
(void)fclose(f);
|
|
return;
|
|
}
|
|
temp = ftell(f);
|
|
if (temp > ROM_SIZE)
|
|
temp = ROM_SIZE;
|
|
(void)fclose(f);
|
|
|
|
/* Adjust BIOS size in chunks of 2K, as per BIOS spec. */
|
|
size = 0x10000;
|
|
if (temp <= 0x8000)
|
|
size = 0x8000;
|
|
if (temp <= 0x4000)
|
|
size = 0x4000;
|
|
if (temp <= 0x2000)
|
|
size = 0x2000;
|
|
mask = (size - 1);
|
|
aha_log("%s: BIOS at 0x%06lX, size %lu, mask %08lx\n",
|
|
dev->name, dev->rom_addr, size, mask);
|
|
|
|
/* Initialize the ROM entry for this BIOS. */
|
|
memset(&dev->bios, 0x00, sizeof(rom_t));
|
|
|
|
/* Enable ROM1 into the memory map. */
|
|
dev->bios.rom = dev->rom1;
|
|
|
|
/* Set up an address mask for this memory. */
|
|
dev->bios.mask = mask;
|
|
|
|
/* Map this system into the memory map. */
|
|
mem_mapping_add(&dev->bios.mapping, dev->rom_addr, size,
|
|
aha_mem_read, NULL, NULL, /* aha_mem_readw, aha_mem_readl, */
|
|
aha_mem_write, NULL, NULL,
|
|
dev->bios.rom, MEM_MAPPING_EXTERNAL, dev);
|
|
mem_mapping_disable(&dev->bios.mapping);
|
|
|
|
/*
|
|
* Patch the ROM BIOS image for stuff Adaptec deliberately
|
|
* made hard to understand. Well, maybe not, maybe it was
|
|
* their way of handling issues like these at the time..
|
|
*
|
|
* Patch 1: emulate the I/O ADDR SW setting by patching a
|
|
* byte in the BIOS that indicates the I/O ADDR
|
|
* switch setting on the board.
|
|
*/
|
|
if (dev->rom_ioaddr != 0x0000) {
|
|
/* Look up the I/O address in the table. */
|
|
for (i=0; i<8; i++)
|
|
if (aha_ports[i] == dev->Base) break;
|
|
if (i == 8) {
|
|
aha_log("%s: invalid I/O address %04x selected!\n",
|
|
dev->name, dev->Base);
|
|
return;
|
|
}
|
|
dev->bios.rom[dev->rom_ioaddr] = (uint8_t)i;
|
|
/* Negation of the DIP switches to satify the checksum. */
|
|
dev->bios.rom[dev->rom_ioaddr + 1] = (uint8_t)((i ^ 0xff) + 1);
|
|
}
|
|
}
|
|
|
|
|
|
static void
|
|
aha_initnvr(x54x_t *dev)
|
|
{
|
|
/* Initialize the on-board EEPROM. */
|
|
dev->nvr[0] = dev->HostID; /* SCSI ID 7 */
|
|
dev->nvr[0] |= (0x10 | 0x20 | 0x40);
|
|
dev->nvr[1] = dev->Irq-9; /* IRQ15 */
|
|
dev->nvr[1] |= (dev->DmaChannel<<4); /* DMA6 */
|
|
dev->nvr[2] = (EE2_HABIOS | /* BIOS enabled */
|
|
EE2_DYNSCAN | /* scan bus */
|
|
EE2_EXT1G | EE2_RMVOK); /* Imm return on seek */
|
|
dev->nvr[3] = SPEED_50; /* speed 5.0 MB/s */
|
|
dev->nvr[6] = (EE6_TERM | /* host term enable */
|
|
EE6_RSTBUS); /* reset SCSI bus on boot*/
|
|
}
|
|
|
|
|
|
/* Initialize the board's EEPROM (NVR.) */
|
|
static void
|
|
aha_setnvr(x54x_t *dev)
|
|
{
|
|
FILE *f;
|
|
|
|
/* Only if this device has an EEPROM. */
|
|
if (dev->nvr_path == NULL) return;
|
|
|
|
/* Allocate and initialize the EEPROM. */
|
|
dev->nvr = (uint8_t *)malloc(NVR_SIZE);
|
|
memset(dev->nvr, 0x00, NVR_SIZE);
|
|
|
|
f = nvr_fopen(dev->nvr_path, L"rb");
|
|
if (f)
|
|
{
|
|
fread(dev->nvr, 1, NVR_SIZE, f);
|
|
fclose(f);
|
|
f = NULL;
|
|
}
|
|
else
|
|
{
|
|
aha_initnvr(dev);
|
|
}
|
|
}
|
|
|
|
|
|
/* General initialization routine for all boards. */
|
|
static void *
|
|
aha_init(device_t *info)
|
|
{
|
|
x54x_t *dev;
|
|
|
|
/* Call common initializer. */
|
|
dev = x54x_init(info);
|
|
|
|
/*
|
|
* Set up the (initial) I/O address, IRQ and DMA info.
|
|
*
|
|
* Note that on MCA, configuration is handled by the BIOS,
|
|
* and so any info we get here will be overwritten by the
|
|
* MCA-assigned values later on!
|
|
*/
|
|
dev->Base = device_get_config_hex16("base");
|
|
dev->Irq = device_get_config_int("irq");
|
|
dev->DmaChannel = device_get_config_int("dma");
|
|
dev->rom_addr = device_get_config_hex20("bios_addr");
|
|
dev->HostID = 7; /* default HA ID */
|
|
dev->setup_info_len = sizeof(aha_setup_t);
|
|
dev->max_id = 7;
|
|
dev->int_geom_writable = 0;
|
|
dev->cdrom_boot = 0;
|
|
dev->bit32 = 0;
|
|
|
|
dev->ven_thread = aha_thread;
|
|
dev->ven_cmd_is_fast = aha_cmd_is_fast;
|
|
dev->ven_fast_cmds = aha_fast_cmds;
|
|
dev->get_ven_param_len = aha_param_len;
|
|
dev->ven_cmds = aha_cmds;
|
|
dev->get_ven_data = aha_setup_data;
|
|
|
|
strcpy(dev->vendor, "Adaptec");
|
|
|
|
/* Perform per-board initialization. */
|
|
switch(dev->type) {
|
|
case AHA_154xB:
|
|
strcpy(dev->name, "AHA-154xB");
|
|
switch(dev->Base) {
|
|
case 0x0330:
|
|
dev->bios_path =
|
|
L"roms/scsi/adaptec/aha1540b320_330.bin";
|
|
break;
|
|
|
|
case 0x0334:
|
|
dev->bios_path =
|
|
L"roms/scsi/adaptec/aha1540b320_334.bin";
|
|
break;
|
|
}
|
|
dev->fw_rev = "A001";
|
|
/* This is configurable from the configuration for the 154xB, the rest of the controllers read it from the EEPROM. */
|
|
dev->HostID = device_get_config_int("hostid");
|
|
break;
|
|
|
|
case AHA_154xC:
|
|
strcpy(dev->name, "AHA-154xC");
|
|
dev->bios_path = L"roms/scsi/adaptec/aha1542c102.bin";
|
|
dev->nvr_path = L"aha1542c.nvr";
|
|
dev->fw_rev = "D001";
|
|
dev->rom_shram = 0x3F80; /* shadow RAM address base */
|
|
dev->rom_shramsz = 128; /* size of shadow RAM */
|
|
dev->rom_ioaddr = 0x3F7E; /* [2:0] idx into addr table */
|
|
dev->rom_fwhigh = 0x0022; /* firmware version (hi/lo) */
|
|
dev->ven_get_host_id = aha_get_host_id; /* function to return host ID from EEPROM */
|
|
dev->ven_get_irq = aha_get_irq; /* function to return IRQ from EEPROM */
|
|
dev->ven_get_dma = aha_get_dma; /* function to return DMA channel from EEPROM */
|
|
break;
|
|
|
|
case AHA_154xCF:
|
|
strcpy(dev->name, "AHA-154xCF");
|
|
dev->bios_path = L"roms/scsi/adaptec/aha1542cf211.bin";
|
|
dev->nvr_path = L"aha1542cf.nvr";
|
|
dev->fw_rev = "E001";
|
|
dev->rom_shram = 0x3F80; /* shadow RAM address base */
|
|
dev->rom_shramsz = 128; /* size of shadow RAM */
|
|
dev->rom_ioaddr = 0x3F7E; /* [2:0] idx into addr table */
|
|
dev->rom_fwhigh = 0x0022; /* firmware version (hi/lo) */
|
|
dev->cdrom_boot = 1;
|
|
dev->ven_get_host_id = aha_get_host_id; /* function to return host ID from EEPROM */
|
|
dev->ven_get_irq = aha_get_irq; /* function to return IRQ from EEPROM */
|
|
dev->ven_get_dma = aha_get_dma; /* function to return DMA channel from EEPROM */
|
|
break;
|
|
|
|
case AHA_154xCP:
|
|
strcpy(dev->name, "AHA-154xCP");
|
|
dev->bios_path = L"roms/scsi/adaptec/aha1542cp102.bin";
|
|
dev->nvr_path = L"aha1540cp.nvr";
|
|
dev->fw_rev = "F001";
|
|
dev->rom_shram = 0x3F80; /* shadow RAM address base */
|
|
dev->rom_shramsz = 128; /* size of shadow RAM */
|
|
dev->rom_ioaddr = 0x3F7E; /* [2:0] idx into addr table */
|
|
dev->rom_fwhigh = 0x0055; /* firmware version (hi/lo) */
|
|
dev->ven_get_host_id = aha_get_host_id; /* function to return host ID from EEPROM */
|
|
dev->ven_get_irq = aha_get_irq; /* function to return IRQ from EEPROM */
|
|
dev->ven_get_dma = aha_get_dma; /* function to return DMA channel from EEPROM */
|
|
break;
|
|
|
|
case AHA_1640:
|
|
strcpy(dev->name, "AHA-1640");
|
|
dev->bios_path = L"roms/scsi/adaptec/aha1640.bin";
|
|
dev->fw_rev = "BB01";
|
|
|
|
/* Enable MCA. */
|
|
dev->pos_regs[0] = 0x1F; /* MCA board ID */
|
|
dev->pos_regs[1] = 0x0F;
|
|
mca_add(aha_mca_read, aha_mca_write, dev);
|
|
break;
|
|
}
|
|
|
|
/* Initialize ROM BIOS if needed. */
|
|
aha_setbios(dev);
|
|
|
|
/* Initialize EEPROM (NVR) if needed. */
|
|
aha_setnvr(dev);
|
|
|
|
if (dev->Base != 0) {
|
|
/* Initialize the device. */
|
|
x54x_device_reset(dev);
|
|
|
|
if (!(dev->bus & DEVICE_MCA)) {
|
|
/* Register our address space. */
|
|
x54x_io_set(dev, dev->Base, 4);
|
|
|
|
/* Enable the memory. */
|
|
if (dev->rom_addr != 0x000000) {
|
|
mem_mapping_enable(&dev->bios.mapping);
|
|
mem_mapping_set_addr(&dev->bios.mapping, dev->rom_addr, ROM_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
return(dev);
|
|
}
|
|
|
|
|
|
static device_config_t aha_154xb_config[] = {
|
|
{
|
|
"base", "Address", CONFIG_HEX16, "", 0x334,
|
|
{
|
|
{
|
|
"None", 0
|
|
},
|
|
{
|
|
"0x330", 0x330
|
|
},
|
|
{
|
|
"0x334", 0x334
|
|
},
|
|
{
|
|
"0x230", 0x230
|
|
},
|
|
{
|
|
"0x234", 0x234
|
|
},
|
|
{
|
|
"0x130", 0x130
|
|
},
|
|
{
|
|
"0x134", 0x134
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"irq", "IRQ", CONFIG_SELECTION, "", 9,
|
|
{
|
|
{
|
|
"IRQ 9", 9
|
|
},
|
|
{
|
|
"IRQ 10", 10
|
|
},
|
|
{
|
|
"IRQ 11", 11
|
|
},
|
|
{
|
|
"IRQ 12", 12
|
|
},
|
|
{
|
|
"IRQ 14", 14
|
|
},
|
|
{
|
|
"IRQ 15", 15
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"dma", "DMA channel", CONFIG_SELECTION, "", 6,
|
|
{
|
|
{
|
|
"DMA 5", 5
|
|
},
|
|
{
|
|
"DMA 6", 6
|
|
},
|
|
{
|
|
"DMA 7", 7
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"hostid", "Host ID", CONFIG_SELECTION, "", 7,
|
|
{
|
|
{
|
|
"0", 0
|
|
},
|
|
{
|
|
"1", 1
|
|
},
|
|
{
|
|
"2", 2
|
|
},
|
|
{
|
|
"3", 3
|
|
},
|
|
{
|
|
"4", 4
|
|
},
|
|
{
|
|
"5", 5
|
|
},
|
|
{
|
|
"6", 6
|
|
},
|
|
{
|
|
"7", 7
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"bios_addr", "BIOS Address", CONFIG_HEX20, "", 0,
|
|
{
|
|
{
|
|
"Disabled", 0
|
|
},
|
|
{
|
|
"C800H", 0xc8000
|
|
},
|
|
{
|
|
"D000H", 0xd0000
|
|
},
|
|
{
|
|
"D800H", 0xd8000
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"", "", -1
|
|
}
|
|
};
|
|
|
|
|
|
static device_config_t aha_154x_config[] = {
|
|
{
|
|
"base", "Address", CONFIG_HEX16, "", 0x334,
|
|
{
|
|
{
|
|
"None", 0
|
|
},
|
|
{
|
|
"0x330", 0x330
|
|
},
|
|
{
|
|
"0x334", 0x334
|
|
},
|
|
{
|
|
"0x230", 0x230
|
|
},
|
|
{
|
|
"0x234", 0x234
|
|
},
|
|
{
|
|
"0x130", 0x130
|
|
},
|
|
{
|
|
"0x134", 0x134
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"irq", "IRQ", CONFIG_SELECTION, "", 9,
|
|
{
|
|
{
|
|
"IRQ 9", 9
|
|
},
|
|
{
|
|
"IRQ 10", 10
|
|
},
|
|
{
|
|
"IRQ 11", 11
|
|
},
|
|
{
|
|
"IRQ 12", 12
|
|
},
|
|
{
|
|
"IRQ 14", 14
|
|
},
|
|
{
|
|
"IRQ 15", 15
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"dma", "DMA channel", CONFIG_SELECTION, "", 6,
|
|
{
|
|
{
|
|
"DMA 5", 5
|
|
},
|
|
{
|
|
"DMA 6", 6
|
|
},
|
|
{
|
|
"DMA 7", 7
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"bios_addr", "BIOS Address", CONFIG_HEX20, "", 0,
|
|
{
|
|
{
|
|
"Disabled", 0
|
|
},
|
|
{
|
|
"C800H", 0xc8000
|
|
},
|
|
{
|
|
"D000H", 0xd0000
|
|
},
|
|
{
|
|
"D800H", 0xd8000
|
|
},
|
|
{
|
|
""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
"", "", -1
|
|
}
|
|
};
|
|
|
|
|
|
device_t aha1540b_device = {
|
|
"Adaptec AHA-1540B",
|
|
DEVICE_ISA | DEVICE_AT,
|
|
AHA_154xB,
|
|
aha_init, x54x_close, NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
aha_154xb_config
|
|
};
|
|
|
|
device_t aha1542c_device = {
|
|
"Adaptec AHA-1542C",
|
|
DEVICE_ISA | DEVICE_AT,
|
|
AHA_154xC,
|
|
aha_init, x54x_close, NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
aha_154x_config
|
|
};
|
|
|
|
device_t aha1542cf_device = {
|
|
"Adaptec AHA-1542CF",
|
|
DEVICE_ISA | DEVICE_AT,
|
|
AHA_154xCF,
|
|
aha_init, x54x_close, NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
aha_154x_config
|
|
};
|
|
|
|
device_t aha1640_device = {
|
|
"Adaptec AHA-1640",
|
|
DEVICE_MCA,
|
|
AHA_1640,
|
|
aha_init, x54x_close, NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
NULL
|
|
};
|