dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/* Copyright holders: Sarah Walker, Tenshi
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see COPYING for more details
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*/
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void fdc_init();
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void fdc_add();
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void fdc_add_for_superio();
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void fdc_add_pcjr();
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void fdc_add_tandy();
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void fdc_remove();
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void fdc_reset();
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void fdc_poll();
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void fdc_abort();
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void fdc_discchange_clear(int drive);
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void fdc_set_dskchg_activelow();
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void fdc_3f1_enable(int enable);
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void fdc_set_ps1();
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int fdc_get_bit_rate();
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int fdc_get_bitcell_period();
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/* A few functions to communicate between Super I/O chips and the FDC. */
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void fdc_update_is_nsc(int is_nsc);
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void fdc_update_max_track(int max_track);
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void fdc_update_enh_mode(int enh_mode);
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int fdc_get_rwc(int drive);
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void fdc_update_rwc(int drive, int rwc);
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int fdc_get_boot_drive();
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void fdc_update_boot_drive(int boot_drive);
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void fdc_update_densel_polarity(int densel_polarity);
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uint8_t fdc_get_densel_polarity();
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void fdc_update_densel_force(int densel_force);
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void fdc_update_drvrate(int drive, int drvrate);
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void fdc_update_drv2en(int drv2en);
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void fdc_noidam();
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void fdc_nosector();
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void fdc_nodataam();
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void fdc_cannotformat();
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void fdc_wrongcylinder();
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void fdc_badcylinder();
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sector_id_t fdc_get_read_track_sector();
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int fdc_get_compare_condition();
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int fdc_is_deleted();
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int fdc_is_sk();
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void fdc_set_wrong_am();
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int fdc_get_drive();
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int fdc_get_perp();
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int fdc_get_format_n();
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int fdc_is_mfm();
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double fdc_get_hut();
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double fdc_get_hlt();
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void fdc_request_next_sector_id();
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void fdc_stop_id_request();
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int fdc_get_gap();
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int fdc_get_gap2(int drive);
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int fdc_get_dtl();
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int fdc_get_format_sectors();
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void fdc_finishcompare(int satisfying);
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void fdc_finishread();
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void fdc_sector_finishcompare(int satisfying);
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void fdc_sector_finishread();
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void fdc_track_finishread(int condition);
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int fdc_is_verify();
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int real_drive(int drive);
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