Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
231 lines
3.8 KiB
C
231 lines
3.8 KiB
C
/* Copyright holders: Tenshi
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see COPYING for more details
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*/
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/*
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SiS sis85c471 Super I/O Chip
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Used by Batman's Revenge
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*/
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#include "ibm.h"
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#include "ide.h"
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#include "disc.h"
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#include "fdc.h"
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#include "fdd.h"
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#include "io.h"
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#include "lpt.h"
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#include "serial.h"
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#include "sis85c471.h"
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static int sis85c471_curreg;
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static uint8_t sis85c471_regs[39];
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void sis85c471_write(uint16_t port, uint8_t val, void *priv)
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{
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uint8_t index = (port & 1) ? 0 : 1;
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int temp;
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uint8_t x;
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// pclog("sis85c471_write : port=%04x reg %02X = %02X\n", port, sis85c471_curreg, val);
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if (index)
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{
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if ((val >= 0x50) && (val <= 0x76)) sis85c471_curreg = val;
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return;
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}
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else
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{
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if ((sis85c471_curreg < 0x50) || (sis85c471_curreg > 0x76)) return;
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x = val ^ sis85c471_regs[sis85c471_curreg - 0x50];
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/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
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if (sis85c471_curreg != 0x52) sis85c471_regs[sis85c471_curreg - 0x50] = val;
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goto process_value;
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}
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return;
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process_value:
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switch(sis85c471_curreg)
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{
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case 0x73:
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#if 0
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if (x & 0x40)
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{
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if (val & 0x40)
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ide_pri_enable();
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else
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ide_pri_disable();
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}
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#endif
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if (x & 0x20)
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{
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if (val & 0x20)
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{
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serial1_init(0x3f8, 4);
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serial2_init(0x2f8, 3);
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}
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else
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{
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serial1_remove();
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serial2_remove();
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}
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}
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if (x & 0x10)
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{
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if (val & 0x10)
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lpt1_init(0x378);
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else
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lpt1_remove();
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}
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break;
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}
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sis85c471_curreg = 0;
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}
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uint8_t sis85c471_read(uint16_t port, void *priv)
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{
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// pclog("sis85c471_read : port=%04x reg %02X\n", port, sis85c471_curreg);
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t temp;
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if (index)
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return sis85c471_curreg;
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else
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if ((sis85c471_curreg >= 0x50) && (sis85c471_curreg <= 0x76))
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{
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temp = sis85c471_regs[sis85c471_curreg - 0x50];
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sis85c471_curreg = 0;
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return temp;
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}
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else
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return 0xFF;
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}
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void sis85c471_init()
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{
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int i = 0;
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// pclog("SiS 85c471 Init\n");
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// ide_sec_disable();
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lpt2_remove();
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sis85c471_curreg = 0;
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for (i = 0; i < 0x27; i++)
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{
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sis85c471_regs[i] = 0;
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}
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sis85c471_regs[9] = 0x40;
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switch (mem_size)
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{
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case 0:
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case 1:
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sis85c471_regs[9] |= 0;
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break;
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case 2:
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case 3:
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sis85c471_regs[9] |= 1;
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break;
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case 4:
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sis85c471_regs[9] |= 2;
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break;
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case 5:
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sis85c471_regs[9] |= 0x20;
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break;
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case 6:
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case 7:
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sis85c471_regs[9] |= 9;
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break;
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case 8:
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case 9:
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sis85c471_regs[9] |= 4;
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break;
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case 10:
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case 11:
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sis85c471_regs[9] |= 5;
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break;
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case 12:
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case 13:
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case 14:
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case 15:
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sis85c471_regs[9] |= 0xB;
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break;
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case 16:
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sis85c471_regs[9] |= 0x13;
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break;
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case 17:
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sis85c471_regs[9] |= 0x21;
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break;
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case 18:
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case 19:
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sis85c471_regs[9] |= 6;
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break;
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case 20:
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case 21:
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case 22:
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case 23:
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sis85c471_regs[9] |= 0xD;
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break;
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case 24:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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sis85c471_regs[9] |= 0xE;
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break;
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case 32:
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case 33:
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case 34:
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case 35:
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sis85c471_regs[9] |= 0x1B;
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break;
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case 36:
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case 37:
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case 38:
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case 39:
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sis85c471_regs[9] |= 0xF;
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break;
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case 40:
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case 41:
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case 42:
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case 43:
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case 44:
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case 45:
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case 46:
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case 47:
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sis85c471_regs[9] |= 0x17;
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break;
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case 48:
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sis85c471_regs[9] |= 0x1E;
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break;
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default:
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if (mem_size < 64)
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{
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sis85c471_regs[9] |= 0x1E;
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}
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else if ((mem_size >= 65) && (mem_size < 68))
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{
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sis85c471_regs[9] |= 0x22;
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}
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else
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{
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sis85c471_regs[9] |= 0x24;
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}
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break;
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}
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sis85c471_regs[0x11] = 9;
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sis85c471_regs[0x12] = 0xFF;
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sis85c471_regs[0x23] = 0xF0;
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sis85c471_regs[0x26] = 1;
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fdc_update_densel_polarity(1);
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fdc_update_densel_force(0);
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fdd_swap = 0;
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io_sethandler(0x0022, 0x0002, sis85c471_read, NULL, NULL, sis85c471_write, NULL, NULL, NULL);
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}
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