Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
211 lines
4.0 KiB
C
211 lines
4.0 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Common code to handle all sorts of disk controllers.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2016-2018 Miran Grca.
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* Copyright 2017,2018 Fred N. van Kempen.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/machine.h>
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#include <86box/device.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdd.h>
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int hdc_current;
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#ifdef ENABLE_HDC_LOG
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int hdc_do_log = ENABLE_HDC_LOG;
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static void
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hdc_log(const char *fmt, ...)
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{
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va_list ap;
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if (hdc_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define hdc_log(fmt, ...)
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#endif
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static void *
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null_init(const device_t *info)
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{
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return(NULL);
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}
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static void
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null_close(void *priv)
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{
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}
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static const device_t null_device = {
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"Null HDC", 0, 0,
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null_init, null_close, NULL,
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{ NULL }, NULL, NULL, NULL
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};
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static void *
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inthdc_init(const device_t *info)
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{
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return(NULL);
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}
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static void
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inthdc_close(void *priv)
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{
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}
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static const device_t inthdc_device = {
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"Internal controller", 0, 0,
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inthdc_init, inthdc_close, NULL,
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{ NULL }, NULL, NULL, NULL
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};
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static const struct {
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const char *internal_name;
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const device_t *device;
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} controllers[] = {
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{ "none", &null_device },
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{ "internal", &inthdc_device },
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{ "st506_xt", &st506_xt_xebec_device },
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{ "st506_xt_dtc5150x", &st506_xt_dtc5150x_device },
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{ "st506_xt_st11_m", &st506_xt_st11_m_device },
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{ "st506_xt_wd1002a_wx1", &st506_xt_wd1002a_wx1_device },
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{ "st506_at", &st506_at_wd1003_device },
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{ "st506_xt_st11_r", &st506_xt_st11_r_device },
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{ "st506_xt_wd1002a_27x", &st506_xt_wd1002a_27x_device },
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{ "esdi_at", &esdi_at_wd1007vse1_device },
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{ "ide_isa", &ide_isa_device },
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{ "ide_isa_2ch", &ide_isa_2ch_device },
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{ "xtide_at", &xtide_at_device },
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{ "xtide_at_ps2", &xtide_at_ps2_device },
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{ "xta_wdxt150", &xta_wdxt150_device },
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{ "xtide_acculogic", &xtide_acculogic_device },
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{ "xtide", &xtide_device },
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{ "esdi_mca", &esdi_ps2_device },
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{ "ide_pci", &ide_pci_device },
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{ "ide_pci_2ch", &ide_pci_2ch_device },
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{ "vlb_isa", &ide_vlb_device },
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{ "vlb_isa_2ch", &ide_vlb_2ch_device },
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{ "", NULL }
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};
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/* Initialize the 'hdc_current' value based on configured HDC name. */
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void
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hdc_init(void)
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{
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hdc_log("HDC: initializing..\n");
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/* Zero all the hard disk image arrays. */
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hdd_image_init();
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}
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/* Reset the HDC, whichever one that is. */
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void
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hdc_reset(void)
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{
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hdc_log("HDC: reset(current=%d, internal=%d)\n",
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hdc_current, (machines[machine].flags & MACHINE_HDC) ? 1 : 0);
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/* If we have a valid controller, add its device. */
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if (hdc_current > 1)
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device_add(controllers[hdc_current].device);
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/* Now, add the tertiary and/or quaternary IDE controllers. */
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if (ide_ter_enabled)
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device_add(&ide_ter_device);
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if (ide_qua_enabled)
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device_add(&ide_qua_device);
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}
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char *
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hdc_get_internal_name(int hdc)
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{
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return((char *) controllers[hdc].internal_name);
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}
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int
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hdc_get_from_internal_name(char *s)
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{
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int c = 0;
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while (strlen((char *) controllers[c].internal_name))
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{
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if (!strcmp((char *) controllers[c].internal_name, s))
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return c;
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c++;
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}
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return 0;
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}
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const device_t *
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hdc_get_device(int hdc)
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{
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return(controllers[hdc].device);
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}
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int
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hdc_has_config(int hdc)
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{
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const device_t *dev = hdc_get_device(hdc);
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if (dev == NULL) return(0);
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if (dev->config == NULL) return(0);
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return(1);
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}
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int
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hdc_get_flags(int hdc)
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{
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return(controllers[hdc].device->flags);
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}
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int
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hdc_available(int hdc)
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{
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return(device_available(controllers[hdc].device));
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}
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