9af10bdac3
Apparently the Trantor T130B SCSI controllers has a different way of calculating the timings and removed the scsi_bus_read() calls from the Current SCSI bus status port (Read Port+4). Fixes NT using said controller as well as CD swapping while maintaining the correct accurate CD speed.
112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the NCR 5380 chip made by NCR
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* and used in various controllers.
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*
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*
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*
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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* TheCollector1995, <mariogplayer@gmail.com>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2017-2018 Sarah Walker.
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* Copyright 2017-2018 Fred N. van Kempen.
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* Copyright 2017-2024 TheCollector1995.
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*/
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#ifndef SCSI_NCR5380_H
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#define SCSI_NCR5380_H
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#define NCR_CURDATA 0 /* current SCSI data (read only) */
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#define NCR_OUTDATA 0 /* output data (write only) */
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#define NCR_INITCOMMAND 1 /* initiator command (read/write) */
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#define NCR_MODE 2 /* mode (read/write) */
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#define NCR_TARGETCMD 3 /* target command (read/write) */
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#define NCR_SELENABLE 4 /* select enable (write only) */
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#define NCR_BUSSTATUS 4 /* bus status (read only) */
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#define NCR_STARTDMA 5 /* start DMA send (write only) */
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#define NCR_BUSANDSTAT 5 /* bus and status (read only) */
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#define NCR_DMATARGET 6 /* DMA target (write only) */
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#define NCR_INPUTDATA 6 /* input data (read only) */
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#define NCR_DMAINIRECV 7 /* DMA initiator receive (write only) */
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#define NCR_RESETPARITY 7 /* reset parity/interrupt (read only) */
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#define ICR_DBP 0x01
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#define ICR_ATN 0x02
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#define ICR_SEL 0x04
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#define ICR_BSY 0x08
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#define ICR_ACK 0x10
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#define ICR_ARB_LOST 0x20
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#define ICR_ARB_IN_PROGRESS 0x40
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#define ICR_RST 0x80
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#define ICR_PHASE 0x9e
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#define ICR_WRITE 0x9f
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#define MODE_ARBITRATE 0x01
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#define MODE_DMA 0x02
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#define MODE_MONITOR_BUSY 0x04
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#define MODE_ENA_EOP_INT 0x08
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#define STATUS_ACK 0x01
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#define STATUS_BUSY_ERROR 0x04
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#define STATUS_PHASE_MATCH 0x08
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#define STATUS_INT 0x10
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#define STATUS_DRQ 0x40
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#define STATUS_END_OF_DMA 0x80
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#define TCR_IO 0x01
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#define TCR_CD 0x02
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#define TCR_MSG 0x04
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#define TCR_REQ 0x08
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#define TCR_LAST_BYTE_SENT 0x80
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typedef struct ncr_t {
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uint8_t icr;
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uint8_t mode;
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uint8_t tcr;
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uint8_t isr;
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uint8_t output_data;
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uint8_t tx_data;
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uint8_t irq_state;
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uint8_t isr_reg;
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uint8_t bus;
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int irq;
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double period;
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void *priv;
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void (*dma_mode_ext)(void *priv, void *ext_priv, uint8_t val);
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int (*dma_send_ext)(void *priv, void *ext_priv);
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int (*dma_initiator_receive_ext)(void *priv, void *ext_priv);
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void (*timer)(void *ext_priv, double period);
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scsi_bus_t scsibus;
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} ncr_t;
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extern void ncr5380_irq(ncr_t *ncr, int set_irq);
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extern void ncr5380_set_irq(ncr_t *ncr, int irq);
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extern uint32_t ncr5380_get_bus_host(ncr_t *ncr);
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extern void ncr5380_write(uint16_t port, uint8_t val, ncr_t *ncr);
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extern uint8_t ncr5380_read(uint16_t port, ncr_t *ncr);
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#ifdef EMU_DEVICE_H
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extern const device_t scsi_lcs6821n_device;
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extern const device_t scsi_pas_device;
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extern const device_t scsi_rt1000b_device;
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extern const device_t scsi_rt1000mc_device;
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extern const device_t scsi_t128_device;
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extern const device_t scsi_t228_device;
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extern const device_t scsi_t130b_device;
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extern const device_t scsi_ls2000_device;
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#endif
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#endif /*SCSI_NCR5380_H*/
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