640 lines
18 KiB
C
640 lines
18 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of the SFF-8038i IDE Bus Master.
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*
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* PRD format :
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* word 0 - base address
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* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
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*
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*
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*
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2020 Sarah Walker.
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* Copyright 2016-2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/cdrom.h>
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#include <86box/hdd.h>
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#include <86box/scsi_device.h>
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#include <86box/scsi_disk.h>
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#include <86box/scsi_cdrom.h>
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#include <86box/dma.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/rdisk.h>
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#include <86box/mo.h>
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#include <86box/plat_unused.h>
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static int next_id = 0;
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uint8_t sff_bus_master_read(uint16_t port, void *priv);
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static uint16_t sff_bus_master_readw(uint16_t port, void *priv);
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static uint32_t sff_bus_master_readl(uint16_t port, void *priv);
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void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
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static void sff_bus_master_writew(uint16_t port, uint16_t val, void *priv);
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static void sff_bus_master_writel(uint16_t port, uint32_t val, void *priv);
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#ifdef ENABLE_SFF_LOG
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int sff_do_log = ENABLE_SFF_LOG;
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static void
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sff_log(const char *fmt, ...)
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{
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va_list ap;
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if (sff_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define sff_log(fmt, ...)
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#endif
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void
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sff_bus_master_handler(sff8038i_t *dev, int enabled, uint16_t base)
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{
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if (dev->enabled && (dev->base != 0x0000)) {
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io_removehandler(dev->base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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}
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if (enabled && (base != 0x0000)) {
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io_sethandler(base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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}
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dev->enabled = enabled;
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dev->base = base;
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}
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static void
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sff_bus_master_next_addr(sff8038i_t *dev)
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{
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dma_bm_read(dev->ptr_cur, (uint8_t *) &(dev->addr), 4, 4);
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dma_bm_read(dev->ptr_cur + 4, (uint8_t *) &(dev->count), 4, 4);
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sff_log("SFF-8038i Bus master DWORDs: %08X %08X\n", dev->addr, dev->count);
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dev->eot = dev->count >> 31;
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dev->count &= 0xfffe;
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if (!dev->count)
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dev->count = 65536;
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dev->addr &= 0xfffffffe;
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dev->ptr_cur += 8;
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}
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void
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sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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#ifdef ENABLE_SFF_LOG
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int channel = (port & 8) ? 1 : 0;
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#endif
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sff_log("SFF-8038i Bus master BYTE write: %04X %02X\n", port, val);
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if (dev->ven_write != NULL)
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val = dev->ven_write(port, val, dev->priv);
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switch (port & 7) {
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case 0:
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sff_log("sff Cmd : val = %02X, old = %02X\n", val, dev->command);
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if ((val & 1) && !(dev->command & 1)) { /*Start*/
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sff_log("sff Bus Master start on channel %i\n", channel);
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dev->ptr_cur = dev->ptr;
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sff_bus_master_next_addr(dev);
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dev->status |= 1;
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}
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if (!(val & 1) && (dev->command & 1)) { /*Stop*/
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sff_log("sff Bus Master stop on channel %i\n", channel);
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dev->status &= ~1;
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}
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dev->command = val;
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break;
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case 1:
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dev->dma_mode = val & 0x03;
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break;
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case 2:
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sff_log("sff Status: val = %02X, old = %02X\n", val, dev->status);
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dev->status &= 0x07;
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dev->status |= (val & 0x60);
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if (val & 0x04)
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dev->status &= ~0x04;
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if (val & 0x02)
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dev->status &= ~0x02;
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffffff00) | (val & 0xfc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val;
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break;
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case 5:
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dev->ptr = (dev->ptr & 0xffff00fc) | (val << 8);
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dev->ptr %= (mem_size * 1024);
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break;
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case 6:
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dev->ptr = (dev->ptr & 0xff00fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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case 7:
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dev->ptr = (dev->ptr & 0x00fffffc) | (val << 24);
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dev->ptr %= (mem_size * 1024);
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break;
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default:
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break;
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}
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}
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static void
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sff_bus_master_writew(uint16_t port, uint16_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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sff_log("SFF-8038i Bus master WORD write: %04X %04X\n", port, val);
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switch (port & 7) {
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case 0:
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case 1:
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case 2:
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sff_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffff0000) | (val & 0xfffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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case 6:
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dev->ptr = (dev->ptr & 0x0000fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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default:
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break;
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}
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}
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static void
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sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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sff_log("SFF-8038i Bus master DWORD write: %04X %08X\n", port, val);
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switch (port & 7) {
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case 0:
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case 1:
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case 2:
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sff_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (val & 0xfffffffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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default:
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break;
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}
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}
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uint8_t
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sff_bus_master_read(uint16_t port, void *priv)
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{
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const sff8038i_t *dev = (sff8038i_t *) priv;
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uint8_t ret = 0xff;
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switch (port & 7) {
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case 0:
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ret = dev->command;
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break;
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case 1:
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ret = dev->dma_mode & 0x03;
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break;
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case 2:
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ret = dev->status & 0x67;
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break;
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case 4:
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ret = dev->ptr0;
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break;
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case 5:
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ret = dev->ptr >> 8;
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break;
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case 6:
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ret = dev->ptr >> 16;
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break;
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case 7:
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ret = dev->ptr >> 24;
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break;
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default:
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break;
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}
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if (dev->ven_read != NULL)
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ret= dev->ven_read(port, ret, dev->priv);
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sff_log("SFF-8038i Bus master BYTE read : %04X %02X\n", port, ret);
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return ret;
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}
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static uint16_t
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sff_bus_master_readw(uint16_t port, void *priv)
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{
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const sff8038i_t *dev = (sff8038i_t *) priv;
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uint16_t ret = 0xffff;
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switch (port & 7) {
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case 0:
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case 1:
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case 2:
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ret = (uint16_t) sff_bus_master_read(port, priv);
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break;
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case 4:
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ret = dev->ptr0 | (dev->ptr & 0xff00);
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break;
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case 6:
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ret = dev->ptr >> 16;
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break;
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default:
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break;
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}
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sff_log("SFF-8038i Bus master WORD read : %04X %04X\n", port, ret);
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return ret;
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}
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static uint32_t
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sff_bus_master_readl(uint16_t port, void *priv)
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{
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const sff8038i_t *dev = (sff8038i_t *) priv;
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uint32_t ret = 0xffffffff;
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switch (port & 7) {
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case 0:
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case 1:
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case 2:
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ret = (uint32_t) sff_bus_master_read(port, priv);
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break;
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case 4:
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ret = dev->ptr0 | (dev->ptr & 0xffffff00);
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break;
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default:
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break;
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}
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sff_log("sff Bus master DWORD read : %04X %08X\n", port, ret);
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return ret;
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}
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int
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sff_bus_master_dma(uint8_t *data, int transfer_length, int total_length, int out, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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#ifdef ENABLE_SFF_LOG
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char *sop;
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#endif
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int force_end = 0;
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int buffer_pos = 0;
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#ifdef ENABLE_SFF_LOG
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sop = out ? "Read" : "Writ";
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#endif
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if (!(dev->status & 1)) {
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sff_log("DMA disabled\n");
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return 2; /*DMA disabled*/
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}
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sff_log("SFF-8038i Bus master %s: %i bytes\n", out ? "write" : "read", transfer_length);
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while (1) {
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if (dev->count <= transfer_length) {
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sff_log("%sing %i bytes to %08X\n", sop, dev->count, dev->addr);
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if (out)
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dma_bm_read(dev->addr, (uint8_t *) (data + buffer_pos), dev->count, 4);
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else
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dma_bm_write(dev->addr, (uint8_t *) (data + buffer_pos), dev->count, 4);
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transfer_length -= dev->count;
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buffer_pos += dev->count;
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} else {
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sff_log("%sing %i bytes to %08X\n", sop, transfer_length, dev->addr);
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if (out)
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dma_bm_read(dev->addr, (uint8_t *) (data + buffer_pos), transfer_length, 4);
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else
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dma_bm_write(dev->addr, (uint8_t *) (data + buffer_pos), transfer_length, 4);
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/* Increase addr and decrease count so that resumed transfers do not mess up. */
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dev->addr += transfer_length;
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dev->count -= transfer_length;
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transfer_length = 0;
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force_end = 1;
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}
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if (force_end) {
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sff_log("Total transfer length smaller than sum of all blocks, partial block\n");
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dev->status &= ~2;
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return 1; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
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} else {
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if (!transfer_length && !dev->eot) {
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if (total_length) {
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sff_log("Total transfer length smaller than sum of all blocks, partial transfer\n");
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sff_bus_master_next_addr(dev);
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return 1; /* We have exhausted the data to transfer but there's more blocks left, break. */
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} else {
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sff_log("Total transfer length smaller than sum of all blocks, full block\n");
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dev->status &= ~2;
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return 1; /* We have exhausted the data to transfer but there's more blocks left, break. */
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}
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} else if (transfer_length && dev->eot) {
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sff_log("Total transfer length greater than sum of all blocks\n");
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dev->status |= 2;
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return 0; /* There is data left to transfer but we have reached EOT - return with error. */
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} else if (dev->eot) {
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sff_log("Regular EOT\n");
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dev->status &= ~3;
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return 3; /* We have regularly reached EOT - clear status and break. */
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} else {
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/* We have more to transfer and there are blocks left, get next block. */
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sff_bus_master_next_addr(dev);
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}
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}
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}
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return 1;
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}
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void
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sff_bus_master_set_irq(uint8_t status, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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uint8_t irq = !!(status & 0x04);
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if (!(dev->status & 0x04) || (status & 0x04))
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dev->status = (dev->status & ~0x04) | status;
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switch (dev->irq_mode) {
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default:
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case IRQ_MODE_LEGACY:
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/* Legacy IRQ mode. */
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if (irq)
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picint(1 << dev->irq_line);
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else
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picintc(1 << dev->irq_line);
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break;
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case IRQ_MODE_PCI_IRQ_PIN:
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/* Native PCI IRQ mode with interrupt pin. */
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if (irq)
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pci_set_irq(dev->slot, dev->irq_pin, &dev->irq_state);
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else
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pci_clear_irq(dev->slot, dev->irq_pin, &dev->irq_state);
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break;
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case IRQ_MODE_MIRQ_0 ... IRQ_MODE_MIRQ_3:
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/* MIRQ 0, 1, 2, or 3. */
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if (irq)
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pci_set_mirq(dev->irq_mode & 3, 0, &dev->irq_state);
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else
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pci_clear_mirq(dev->irq_mode & 3, 0, &dev->irq_state);
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break;
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/* TODO: Redo this as a MIRQ. */
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case IRQ_MODE_PCI_IRQ_LINE:
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/* Native PCI IRQ mode with specified interrupt line. */
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if (irq)
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pci_set_dirq(dev->pci_irq_line, &dev->irq_state);
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else
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pci_clear_dirq(dev->pci_irq_line, &dev->irq_state);
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break;
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case IRQ_MODE_ALI_ALADDIN:
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/* ALi Aladdin Native PCI INTAJ mode. */
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if (irq)
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pci_set_mirq((dev->channel + 2), pci_get_mirq_level(dev->channel + 2), &dev->irq_state);
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else
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pci_clear_mirq((dev->channel + 2), pci_get_mirq_level(dev->channel + 2), &dev->irq_state);
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break;
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case IRQ_MODE_SIS_551X:
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/* SiS 551x mode. */
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if (irq)
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pci_set_mirq(dev->mirq, 1, &dev->irq_state);
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else
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pci_clear_mirq(dev->mirq, 1, &dev->irq_state);
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break;
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}
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}
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void
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sff_bus_master_reset(sff8038i_t *dev)
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{
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if (dev->enabled && (dev->base != 0x0000)) {
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io_removehandler(dev->base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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dev->enabled = 0;
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}
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dev->command = 0x00;
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dev->status = 0x00;
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dev->ptr = dev->ptr_cur = 0x00000000;
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dev->addr = 0x00000000;
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dev->ptr0 = 0x00;
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dev->count = dev->eot = 0x00000000;
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dev->irq_state = 0;
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ide_pri_disable();
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ide_sec_disable();
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}
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static void
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sff_reset(void *priv)
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{
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#ifdef ENABLE_SFF_LOG
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sff_log("SFF8038i: Reset\n");
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#endif
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for (uint8_t i = 0; i < HDD_NUM; i++) {
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if ((hdd[i].bus_type == HDD_BUS_ATAPI) && (hdd[i].ide_channel < 4) && hdd[i].priv)
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scsi_disk_reset((scsi_common_t *) hdd[i].priv);
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}
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for (uint8_t i = 0; i < CDROM_NUM; i++) {
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if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) &&
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cdrom[i].priv)
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scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
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}
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for (uint8_t i = 0; i < RDISK_NUM; i++) {
|
|
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel < 4) &&
|
|
rdisk_drives[i].priv)
|
|
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
|
|
}
|
|
for (uint8_t i = 0; i < MO_NUM; i++) {
|
|
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) &&
|
|
mo_drives[i].priv)
|
|
mo_reset((scsi_common_t *) mo_drives[i].priv);
|
|
}
|
|
|
|
sff_bus_master_set_irq(0x00, priv);
|
|
sff_bus_master_set_irq(0x01, priv);
|
|
}
|
|
|
|
void
|
|
sff_set_slot(sff8038i_t *dev, int slot)
|
|
{
|
|
dev->slot = slot;
|
|
}
|
|
|
|
void
|
|
sff_set_irq_line(sff8038i_t *dev, int pci_irq_line)
|
|
{
|
|
dev->pci_irq_line = pci_irq_line;
|
|
}
|
|
|
|
/* TODO: Why does this always set the level to 0, regardless of the parameter?! */
|
|
void
|
|
sff_set_irq_level(sff8038i_t *dev, UNUSED(int irq_level))
|
|
{
|
|
dev->irq_level = 0;
|
|
}
|
|
|
|
void
|
|
sff_set_irq_mode(sff8038i_t *dev, int irq_mode)
|
|
{
|
|
dev->irq_mode = irq_mode;
|
|
|
|
switch (dev->irq_mode) {
|
|
default:
|
|
case IRQ_MODE_LEGACY:
|
|
/* Legacy IRQ mode. */
|
|
sff_log("[%08X] Setting IRQ mode to legacy IRQ %i\n", dev, dev->irq_line);
|
|
break;
|
|
case IRQ_MODE_PCI_IRQ_PIN:
|
|
/* Native PCI IRQ mode with interrupt pin. */
|
|
sff_log("[%08X] Setting IRQ mode to native PCI INT%c\n", dev, 0x40 + dev->irq_pin);
|
|
break;
|
|
case IRQ_MODE_MIRQ_0 ... IRQ_MODE_MIRQ_3:
|
|
/* MIRQ 0, 1, 2, or 3. */
|
|
sff_log("[%08X] Setting IRQ mode to PCI MIRQ%i\n", dev, dev->irq_mode & 3);
|
|
break;
|
|
case IRQ_MODE_PCI_IRQ_LINE:
|
|
/* Native PCI IRQ mode with specified interrupt line. */
|
|
sff_log("[%08X] Setting IRQ mode to native PCI IRQ %i\n", dev, dev->pci_irq_line);
|
|
break;
|
|
case IRQ_MODE_ALI_ALADDIN:
|
|
/* ALi Aladdin Native PCI INTAJ mode. */
|
|
sff_log("[%08X] Setting IRQ mode to INT%cJ\n", dev, 'A' + dev->channel);
|
|
break;
|
|
case IRQ_MODE_SIS_551X:
|
|
/* SiS 551x mode. */
|
|
sff_log("[%08X] Setting IRQ mode to PCI MIRQ2\n", dev);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
sff_set_irq_pin(sff8038i_t *dev, int irq_pin)
|
|
{
|
|
dev->irq_pin = irq_pin;
|
|
}
|
|
|
|
void
|
|
sff_set_mirq(sff8038i_t *dev, uint8_t mirq)
|
|
{
|
|
dev->mirq = mirq;
|
|
}
|
|
|
|
void
|
|
sff_set_ven_handlers(sff8038i_t *dev, uint8_t (*ven_write)(uint16_t port, uint8_t val, void *priv),
|
|
uint8_t (*ven_read)(uint16_t port, uint8_t val, void *priv), void *priv)
|
|
{
|
|
dev->ven_write = ven_write;
|
|
dev->ven_read = ven_read;
|
|
|
|
dev->priv = priv;
|
|
}
|
|
|
|
static void
|
|
sff_close(void *priv)
|
|
{
|
|
sff8038i_t *dev = (sff8038i_t *) priv;
|
|
|
|
free(dev);
|
|
|
|
next_id--;
|
|
if (next_id < 0)
|
|
next_id = 0;
|
|
}
|
|
|
|
static void *
|
|
sff_init(UNUSED(const device_t *info))
|
|
{
|
|
sff8038i_t *dev = (sff8038i_t *) calloc(1, sizeof(sff8038i_t));
|
|
|
|
/* Make sure to only add IDE once. */
|
|
if (next_id == 0)
|
|
device_add(&ide_pci_2ch_device);
|
|
|
|
ide_set_bus_master(next_id, sff_bus_master_dma, sff_bus_master_set_irq, dev);
|
|
|
|
dev->slot = 7;
|
|
/* Channel 0 goes to IRQ 14, channel 1 goes to MIRQ0. */
|
|
dev->irq_mode = next_id ? IRQ_MODE_MIRQ_0 : IRQ_MODE_LEGACY;
|
|
dev->irq_pin = PCI_INTA;
|
|
dev->irq_line = 14 + next_id;
|
|
dev->pci_irq_line = 14;
|
|
dev->irq_level = 0;
|
|
dev->irq_state = 0;
|
|
dev->mirq = 2;
|
|
|
|
dev->channel = next_id;
|
|
next_id++;
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t sff8038i_device = {
|
|
.name = "SFF-8038i IDE Bus Master",
|
|
.internal_name = "sff8038i",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0,
|
|
.init = sff_init,
|
|
.close = sff_close,
|
|
.reset = sff_reset,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|