697 lines
19 KiB
C
697 lines
19 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the CMD PCI-0640B controller.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/cdrom.h>
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#include <86box/scsi_device.h>
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#include <86box/scsi_cdrom.h>
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#include <86box/dma.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/zip.h>
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#include <86box/mo.h>
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typedef struct cmd640_t {
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uint8_t vlb_idx;
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uint8_t id;
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uint8_t in_cfg;
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uint8_t channels;
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uint8_t pci;
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uint8_t irq_state;
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uint8_t pci_slot;
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uint8_t pad0;
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uint8_t regs[256];
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uint32_t local;
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int irq_mode[2];
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int irq_pin;
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int irq_line;
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} cmd640_t;
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static int next_id = 0;
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#ifdef ENABLE_CMD640_LOG
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int cmd640_do_log = ENABLE_CMD640_LOG;
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static void
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cmd640_log(const char *fmt, ...)
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{
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va_list ap;
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if (cmd640_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define cmd640_log(fmt, ...)
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#endif
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void
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cmd640_set_irq_0(uint8_t status, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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int irq = !!(status & 0x04);
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if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
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dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
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if (!(dev->channels & 1))
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return;
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if (irq) {
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if (dev->irq_mode[0] == 1)
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pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
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else
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picint(1 << 14);
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} else {
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if (dev->irq_mode[0] == 1)
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pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
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else
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picintc(1 << 14);
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}
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}
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void
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cmd640_set_irq_1(uint8_t status, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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int irq = !!(status & 0x04);
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if (!(dev->regs[0x57] & 0x10) || (status & 0x04))
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dev->regs[0x57] = (dev->regs[0x57] & ~0x10) | (status << 2);
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if (!(dev->channels & 2))
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return;
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if (irq) {
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if (dev->irq_mode[1] == 1)
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pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
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else
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picint(1 << 15);
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} else {
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if (dev->irq_mode[1] == 1)
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pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
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else
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picintc(1 << 15);
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}
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}
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static void
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cmd640_ide_handlers(cmd640_t *dev)
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{
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uint16_t main;
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uint16_t side;
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if (dev->channels & 0x01) {
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ide_pri_disable();
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if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
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main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
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side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
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} else {
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main = 0x1f0;
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side = 0x3f6;
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}
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ide_set_base(0, main);
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ide_set_side(0, side);
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if (dev->regs[0x04] & 0x01)
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ide_pri_enable();
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}
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if (dev->channels & 0x02) {
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ide_sec_disable();
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if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
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main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
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side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
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} else {
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main = 0x170;
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side = 0x376;
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}
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ide_set_base(1, main);
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ide_set_side(1, side);
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if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
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ide_sec_enable();
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}
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}
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static void
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cmd640_common_write(int addr, uint8_t val, cmd640_t *dev)
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{
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switch (addr) {
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case 0x51:
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dev->regs[addr] = val;
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cmd640_ide_handlers(dev);
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break;
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case 0x52:
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case 0x54:
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case 0x56:
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case 0x58:
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case 0x59:
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dev->regs[addr] = val;
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break;
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case 0x53:
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case 0x55:
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dev->regs[addr] = val & 0xc0;
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break;
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case 0x57:
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dev->regs[addr] = val & 0xdc;
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break;
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case 0x5b: /* Undocumented register that Linux attempts to use! */
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dev->regs[addr] = val;
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break;
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default:
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break;
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}
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}
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static void
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cmd640_vlb_write(uint16_t addr, uint8_t val, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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addr &= 0x00ff;
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switch (addr) {
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case 0x0078:
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if (dev->in_cfg)
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dev->vlb_idx = val;
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else if ((dev->regs[0x50] & 0x80) && (val == dev->id))
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dev->in_cfg = 1;
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break;
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case 0x007c:
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cmd640_common_write(dev->vlb_idx, val, dev);
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if (dev->regs[0x50] & 0x80)
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dev->in_cfg = 0;
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break;
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default:
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break;
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}
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}
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static void
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cmd640_vlb_writew(uint16_t addr, uint16_t val, void *priv)
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{
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cmd640_vlb_write(addr, val & 0xff, priv);
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cmd640_vlb_write(addr + 1, val >> 8, priv);
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}
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static void
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cmd640_vlb_writel(uint16_t addr, uint32_t val, void *priv)
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{
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cmd640_vlb_writew(addr, val & 0xffff, priv);
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cmd640_vlb_writew(addr + 2, val >> 16, priv);
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}
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static uint8_t
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cmd640_vlb_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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cmd640_t *dev = (cmd640_t *) priv;
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addr &= 0x00ff;
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switch (addr) {
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case 0x0078:
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if (dev->in_cfg)
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ret = dev->vlb_idx;
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break;
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case 0x007c:
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ret = dev->regs[dev->vlb_idx];
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if (dev->vlb_idx == 0x50)
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dev->regs[0x50] &= ~0x04;
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else if (dev->vlb_idx == 0x57)
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dev->regs[0x57] &= ~0x10;
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if (dev->regs[0x50] & 0x80)
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dev->in_cfg = 0;
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break;
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default:
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break;
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}
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return ret;
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}
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static uint16_t
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cmd640_vlb_readw(uint16_t addr, void *priv)
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{
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uint16_t ret = 0xffff;
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ret = cmd640_vlb_read(addr, priv);
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ret |= (cmd640_vlb_read(addr + 1, priv) << 8);
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return ret;
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}
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static uint32_t
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cmd640_vlb_readl(uint16_t addr, void *priv)
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{
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uint32_t ret = 0xffffffff;
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ret = cmd640_vlb_readw(addr, priv);
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ret |= (cmd640_vlb_readw(addr + 2, priv) << 16);
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return ret;
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}
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static void
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cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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cmd640_log("cmd640_pci_write(%i, %02X, %02X)\n", func, addr, val);
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if (func == 0x00)
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switch (addr) {
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case 0x04:
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dev->regs[addr] = (val & 0x41);
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cmd640_ide_handlers(dev);
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break;
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case 0x07:
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dev->regs[addr] &= ~(val & 0x80);
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break;
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case 0x09:
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if ((dev->regs[addr] & 0x0a) == 0x0a) {
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dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
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dev->irq_mode[0] = !!(val & 0x01);
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dev->irq_mode[1] = !!(val & 0x04);
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x10:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x10] = (val & 0xf8) | 1;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x11:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x11] = val;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x14:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x14] = (val & 0xfc) | 1;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x15:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x15] = val;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x18:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x18] = (val & 0xf8) | 1;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x19:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x19] = val;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x1c:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x1c] = (val & 0xfc) | 1;
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cmd640_ide_handlers(dev);
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}
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break;
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case 0x1d:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x1d] = val;
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cmd640_ide_handlers(dev);
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}
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break;
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default:
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cmd640_common_write(addr, val, dev);
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break;
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}
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}
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static uint8_t
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cmd640_pci_read(int func, int addr, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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uint8_t ret = 0xff;
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if (func == 0x00) {
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ret = dev->regs[addr];
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if (addr == 0x50)
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dev->regs[0x50] &= ~0x04;
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else if (addr == 0x57)
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dev->regs[0x57] &= ~0x10;
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}
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cmd640_log("cmd640_pci_read(%i, %02X, %02X)\n", func, addr, ret);
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return ret;
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}
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static void
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cmd640_reset(void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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int i = 0;
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int min_channel;
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int max_channel;
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switch (dev->channels) {
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default:
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case 0x00:
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min_channel = max_channel = 0;
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break;
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case 0x01:
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min_channel = 0;
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max_channel = 1;
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break;
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case 0x02:
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min_channel = 2;
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max_channel = 3;
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break;
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case 0x03:
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min_channel = 0;
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max_channel = 3;
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break;
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}
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for (i = 0; i < CDROM_NUM; i++) {
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if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel >= min_channel) &&
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(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
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scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
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}
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for (i = 0; i < ZIP_NUM; i++) {
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if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
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(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
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zip_reset((scsi_common_t *) zip_drives[i].priv);
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}
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for (i = 0; i < MO_NUM; i++) {
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if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
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(mo_drives[i].ide_channel <= max_channel) && mo_drives[i].priv)
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mo_reset((scsi_common_t *) mo_drives[i].priv);
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}
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if (dev->channels & 0x01)
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cmd640_set_irq_0(0x00, priv);
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if (dev->channels & 0x02)
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cmd640_set_irq_1(0x00, priv);
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memset(dev->regs, 0x00, sizeof(dev->regs));
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dev->regs[0x50] = 0x02; /* Revision 02 */
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dev->regs[0x50] |= (dev->id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
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dev->regs[0x59] = 0x40;
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if (dev->pci) {
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cmd640_log("dev->local = %08X\n", dev->local);
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if ((dev->local & 0xffff) == 0x0a) {
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dev->regs[0x50] |= 0x40; /* Enable Base address register R/W;
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If 0, they return 0 and are read-only 8 */
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}
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dev->regs[0x00] = 0x95; /* CMD */
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dev->regs[0x01] = 0x10;
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dev->regs[0x02] = 0x40; /* PCI-0640B */
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dev->regs[0x03] = 0x06;
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dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
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dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
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dev->regs[0x08] = 0x02; /* Revision 02 */
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dev->regs[0x09] = dev->local; /* Programming interface */
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dev->regs[0x0a] = 0x01; /* IDE controller */
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dev->regs[0x0b] = 0x01; /* Mass storage controller */
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/* Base addresses (1F0, 3F4, 170, 374) */
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x10] = 0xf1;
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dev->regs[0x11] = 0x01;
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dev->regs[0x14] = 0xf5;
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dev->regs[0x15] = 0x03;
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dev->regs[0x18] = 0x71;
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dev->regs[0x19] = 0x01;
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dev->regs[0x1c] = 0x75;
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dev->regs[0x1d] = 0x03;
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}
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dev->regs[0x3c] = 0x14; /* IRQ 14 */
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dev->regs[0x3d] = 0x01; /* INTA */
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dev->irq_mode[0] = dev->irq_mode[1] = 0;
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dev->irq_pin = PCI_INTA;
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dev->irq_line = 14;
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} else {
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dev->regs[0x04] = 0x01; /* To make sure the two channels get enabled. */
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if ((dev->local & 0xffff) == 0x0078)
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dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
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/* If bit 7 is 1, then device ID has to be written on port x78h before
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accessing the configuration registers */
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dev->in_cfg = 1; /* Configuration registers are accessible */
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}
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cmd640_ide_handlers(dev);
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}
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static void
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cmd640_close(void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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free(dev);
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next_id = 0;
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}
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static void *
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cmd640_init(const device_t *info)
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{
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cmd640_t *dev = (cmd640_t *) malloc(sizeof(cmd640_t));
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memset(dev, 0x00, sizeof(cmd640_t));
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|
|
|
dev->id = next_id | 0x60;
|
|
|
|
dev->pci = !!(info->flags & DEVICE_PCI);
|
|
dev->local = info->local;
|
|
|
|
dev->channels = ((info->local & 0x60000) >> 17) & 0x03;
|
|
|
|
if (info->flags & DEVICE_PCI) {
|
|
device_add(&ide_pci_2ch_device);
|
|
|
|
if (info->local & 0x80000)
|
|
pci_add_card(PCI_ADD_NORMAL, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
|
|
else
|
|
pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
|
|
|
|
if (dev->channels & 0x01)
|
|
ide_set_bus_master(0, NULL, cmd640_set_irq_0, dev);
|
|
|
|
if (dev->channels & 0x02)
|
|
ide_set_bus_master(1, NULL, cmd640_set_irq_1, dev);
|
|
|
|
/* The CMD PCI-0640B IDE controller has no DMA capability,
|
|
so set our devices IDE devices to force ATA-3 (no DMA). */
|
|
if (dev->channels & 0x01)
|
|
ide_board_set_force_ata3(0, 1);
|
|
|
|
if (dev->channels & 0x02)
|
|
ide_board_set_force_ata3(1, 1);
|
|
|
|
#if 0
|
|
ide_pri_disable();
|
|
#endif
|
|
} else if (info->flags & DEVICE_VLB) {
|
|
device_add(&ide_vlb_2ch_device);
|
|
|
|
io_sethandler(info->local & 0xffff, 0x0008,
|
|
cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl,
|
|
cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel,
|
|
dev);
|
|
}
|
|
|
|
next_id++;
|
|
|
|
cmd640_reset(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t ide_cmd640_vlb_device = {
|
|
.name = "CMD PCI-0640B VLB",
|
|
.internal_name = "ide_cmd640_vlb",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x60078,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_vlb_178_device = {
|
|
.name = "CMD PCI-0640B VLB (Port 178h)",
|
|
.internal_name = "ide_cmd640_vlb_178",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x60178,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_vlb_pri_device = {
|
|
.name = "CMD PCI-0640B VLB",
|
|
.internal_name = "ide_cmd640_vlb",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x20078,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_vlb_pri_178_device = {
|
|
.name = "CMD PCI-0640B VLB (Port 178h)",
|
|
.internal_name = "ide_cmd640_vlb_178",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x20178,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_vlb_sec_device = {
|
|
.name = "CMD PCI-0640B VLB",
|
|
.internal_name = "ide_cmd640_vlb",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x40078,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_vlb_sec_178_device = {
|
|
.name = "CMD PCI-0640B VLB (Port 178h)",
|
|
.internal_name = "ide_cmd640_vlb_178",
|
|
.flags = DEVICE_VLB,
|
|
.local = 0x40178,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_pci_device = {
|
|
.name = "CMD PCI-0640B PCI",
|
|
.internal_name = "ide_cmd640_pci",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x6000a,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_pci_legacy_only_device = {
|
|
.name = "CMD PCI-0640B PCI (Legacy Mode Only)",
|
|
.internal_name = "ide_cmd640_pci_legacy_only",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x60000,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_pci_single_channel_device = {
|
|
.name = "CMD PCI-0640B PCI",
|
|
.internal_name = "ide_cmd640_pci_single_channel",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x2000a,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ide_cmd640_pci_single_channel_sec_device = {
|
|
.name = "CMD PCI-0640B PCI",
|
|
.internal_name = "ide_cmd640_pci_single_channel_sec",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x4000a,
|
|
.init = cmd640_init,
|
|
.close = cmd640_close,
|
|
.reset = cmd640_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|