965 lines
31 KiB
C
965 lines
31 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Sigma Color 400 emulation.
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*
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*
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*
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* Authors: John Elliott,
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*
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* Copyright 2018 John Elliott.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/rom.h>
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#include <86box/device.h>
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#include <86box/video.h>
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#define ROM_SIGMA_FONT "roms/video/sigma/sigma400_font.rom"
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#define ROM_SIGMA_BIOS "roms/video/sigma/sigma400_bios.rom"
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/* The Sigma Designs Color 400 is a video card from 1985, presumably intended
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* as an EGA competitor.
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*
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* The hardware seems to have gone through various iterations; I've seen
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* pictures of full-length and half-length versions.
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* TH99 describes the jumpers / switches:
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* <http://arvutimuuseum.ee/th99/v/S-T/52579.htm>
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*
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* The card is CGA-compatible at BIOS level, but to improve compatibility
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* attempts to write to the CGA I/O ports at 0x3D0-0x3DF trigger an NMI. The
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* card's BIOS handles the NMI and translates the CGA writes into commands
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* to its own hardware at 0x2D0-0x2DF. (DIP switches on the card allow the
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* base address to be changed, but since the BIOS dump I have doesn't support
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* this I haven't emulated it. Likewise the BIOS ROM address can be changed,
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* but I'm going with the default of 0xC0000).
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*
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* The BIOS still functions if the NMI system isn't operational. There
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* doesn't seem to be a jumper or DIP switch to lock it out, but at startup
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* the BIOS tests for its presence and configures itself to work or not
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* as required. I've therefore added a configuration option to handle this.
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*
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* The card's real CRTC at 0x2D0/0x2D1 appears to be a 6845. One oddity is
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* that all its horizontal counts are halved compared to what a real CGA
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* uses; 40-column modes have a width of 20, and 80-column modes have a
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* width of 40. This means that the CRTC cursor position (registers 14/15) can
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* only address even-numbered columns, so the top bit of the control
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* register at 0x2D9 is used to adjust the position.
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*
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* Apart from the CRTC, registers are:
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*
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* 0x2D8: Mode register. Values written by the card BIOS are:
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* Text 40x25: 0xA8
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* Text 80x25: 0xB9
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* Text 80x30: 0xB9
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* Text 80x50: 0x79
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* Graphics 320x200: 0x0F
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* Graphics 640x200: 0x1F
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* Graphics 640x400: 0x7F
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*
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* I have assumed this is a bitmap with the following meaning: */
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#define MODE_80COLS 0x01 /* For text modes, 80 columns across */
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#define MODE_GRAPHICS 0x02 /* Graphics mode */
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#define MODE_NOBLINK 0x04 /* Disable blink? */
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#define MODE_ENABLE 0x08 /* Enable display */
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#define MODE_HRGFX 0x10 /* For graphics modes, 640 pixels across */
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#define MODE_640x400 0x40 /* 400-line graphics mode */
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#define MODE_FONT16 0x80 /* Use 16-pixel high font */
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/*
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* 0x2D9: Control register, with the following bits: */
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#define CTL_CURSOR 0x80 /* Low bit of cursor position */
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#define CTL_NMI 0x20 /* Writes to 0x3D0-0x3DF trigger NMI */
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#define CTL_CLEAR_LPEN 0x08 /* Strobe 0 to clear lightpen latch */
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#define CTL_SET_LPEN 0x04 /* Strobe 0 to set lightpen latch */
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#define CTL_PALETTE 0x01 /* 0x2DE writes to palette (1) or plane (0) */
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/*
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* The card BIOS seems to support two variants of the hardware: One where
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* bits 2 and 3 are normally 1 and are set to 0 to set/clear the latch, and
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* one where they are normally 0 and are set to 1. Behaviour is selected by
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* whether the byte at C000:17FFh is greater than 2Fh.
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*
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* 0x2DA: Status register.
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*/
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#define STATUS_CURSOR 0x80 /* Last value written to bit 7 of 0x2D9 */
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#define STATUS_NMI 0x20 /* Last value written to bit 5 of 0x2D9 */
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#define STATUS_RETR_V 0x10 /* Vertical retrace */
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#define STATUS_LPEN_T 0x04 /* Lightpen switch is off */
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#define STATUS_LPEN_A 0x02 /* Edge from lightpen has set trigger */
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#define STATUS_RETR_H 0x01 /* Horizontal retrace */
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/*
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* 0x2DB: On read: Byte written to the card that triggered NMI
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* 0x2DB: On write: Resets the 'card raised NMI' flag.
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* 0x2DC: On read: Bit 7 set if the card raised NMI. If so, bits 0-3
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* give the low 4 bits of the I/O port address.
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* 0x2DC: On write: Resets the NMI.
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* 0x2DD: Memory paging. The memory from 0xC1800 to 0xC1FFF can be either:
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*
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* > ROM: A 128 character 8x16 font for use in graphics modes
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* > RAM: Use by the video BIOS to hold its settings.
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*
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* Reading port 2DD switches to ROM. Bit 7 of the value read gives the
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* previous paging state: bit 7 set if ROM was paged, clear if RAM was
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* paged.
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*
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* Writing port 2DD switches to RAM.
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*
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* 0x2DE: Meaning depends on bottom bit of value written to port 0x2D9.
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* Bit 0 set: Write to palette. High 4 bits of value = register,
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* low 4 bits = RGBI values (active low)
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* Bit 0 clear: Write to plane select. Low 2 bits of value select
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* plane 0-3
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*/
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typedef struct sigma_t {
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mem_mapping_t mapping, bios_ram;
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rom_t bios_rom;
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uint8_t crtc[32]; /* CRTC: Real values */
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uint8_t lastport; /* Last I/O port written */
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uint8_t lastwrite; /* Value written to that port */
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uint8_t sigma_ctl; /* Controls register:
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* Bit 7 is low bit of cursor position
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* Bit 5 set if writes to CGA ports trigger NMI
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* Bit 3 clears lightpen latch
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* Bit 2 sets lightpen latch
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* Bit 1 controls meaning of port 2DE
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*/
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uint8_t enable_nmi; /* Enable the NMI mechanism for CGA emulation?*/
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uint8_t rom_paged; /* Is ROM paged in at 0xC1800? */
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uint8_t crtc_value; /* Value to return from a CRTC register read */
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uint8_t sigmastat, /* Status register [0x2DA] */
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fake_stat; /* see sigma_in() for comment */
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uint8_t sigmamode; /* Mode control register [0x2D8] */
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uint16_t ma, maback;
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int crtcreg; /* CRTC: Real selected register */
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int linepos, displine;
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int sc, vc;
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int cgadispon;
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int con, coff, cursoron, cgablink;
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int vsynctime, vadj;
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int oddeven;
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uint64_t dispontime, dispofftime;
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int firstline, lastline;
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int drawcursor;
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pc_timer_t timer;
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uint8_t *vram;
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uint8_t bram[2048];
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uint8_t palette[16];
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int plane;
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int revision;
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int fullchange;
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} sigma_t;
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#define COMPOSITE_OLD 0
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#define COMPOSITE_NEW 1
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static uint8_t crtcmask[32] = {
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0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
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0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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static video_timings_t timing_sigma = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
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static void sigma_recalctimings(sigma_t *cga);
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static void
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sigma_out(uint16_t addr, uint8_t val, void *p)
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{
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sigma_t *sigma = (sigma_t *) p;
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uint8_t old;
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if (addr >= 0x3D0 && addr < 0x3E0) {
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sigma->lastport = addr & 0x0F;
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sigma->lastwrite = val;
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/* If set to NMI on video I/O... */
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if (sigma->enable_nmi && (sigma->sigma_ctl & CTL_NMI)) {
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sigma->lastport |= 0x80; /* Card raised NMI */
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nmi_raise();
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}
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/* For CRTC emulation, the card BIOS sets the value to be
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* read from port 0x3D1 like this */
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if (addr == 0x3D1)
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sigma->crtc_value = val;
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} else
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switch (addr) {
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case 0x2D0:
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case 0x2D2:
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case 0x2D4:
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case 0x2D6:
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sigma->crtcreg = val & 31;
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return;
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case 0x2D1:
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case 0x2D3:
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case 0x2D5:
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case 0x2D7:
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old = sigma->crtc[sigma->crtcreg];
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sigma->crtc[sigma->crtcreg] = val & crtcmask[sigma->crtcreg];
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if (old != val) {
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if (sigma->crtcreg < 0xe || sigma->crtcreg > 0x10) {
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sigma->fullchange = changeframecount;
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sigma_recalctimings(sigma);
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}
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}
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return;
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case 0x2D8:
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sigma->sigmamode = val;
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return;
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case 0x2D9:
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sigma->sigma_ctl = val;
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return;
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case 0x2DB:
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sigma->lastport &= 0x7F;
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return;
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case 0x2DC: /* Reset NMI */
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nmi = 0;
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sigma->lastport &= 0x7F;
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return;
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case 0x2DD: /* Page in RAM at 0xC1800 */
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if (sigma->rom_paged != 0)
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mmu_invalidate(0xC0000);
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sigma->rom_paged = 0x00;
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return;
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case 0x2DE:
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if (sigma->sigma_ctl & CTL_PALETTE)
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sigma->palette[val >> 4] = (val & 0x0F) ^ 0x0F;
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else
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sigma->plane = val & 3;
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return;
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}
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}
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static uint8_t
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sigma_in(uint16_t addr, void *p)
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{
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uint8_t result = 0xFF;
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sigma_t *sigma = (sigma_t *) p;
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switch (addr) {
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case 0x2D0:
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case 0x2D2:
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case 0x2D4:
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case 0x2D6:
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result = sigma->crtcreg;
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break;
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case 0x2D1:
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case 0x2D3:
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case 0x2D5:
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case 0x2D7:
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result = sigma->crtc[sigma->crtcreg & 0x1F];
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break;
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case 0x2DA:
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result = (sigma->sigma_ctl & 0xE0) | (sigma->sigmastat & 0x1F);
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break;
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case 0x2DB:
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result = sigma->lastwrite; /* Value that triggered NMI */
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break;
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case 0x2DC:
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result = sigma->lastport; /* Port that triggered NMI */
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break;
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case 0x2DD: /* Page in ROM at 0xC1800 */
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result = (sigma->rom_paged ? 0x80 : 0);
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if (sigma->rom_paged != 0x80)
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mmu_invalidate(0xC0000);
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sigma->rom_paged = 0x80;
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break;
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case 0x3D1:
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case 0x3D3:
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case 0x3D5:
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case 0x3D7:
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result = sigma->crtc_value;
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break;
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/* For CGA compatibility we have to return something palatable on this port.
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On a real card this functionality can be turned on or off with SW1/6 */
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case 0x3DA:
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if (sigma->sigmamode & MODE_ENABLE) {
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result = sigma->sigmastat & 0x07;
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if (sigma->sigmastat & STATUS_RETR_V)
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result |= 0x08;
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} else {
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/*
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* The card is not running yet, and someone
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* (probably the system BIOS) is trying to
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* read our status in CGA mode.
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*
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* One of the systems that do this, is the
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* DTK XT (PIM-10TB-Z board) with ERSO 2.42
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* BIOS. If this test fails (i.e. it doesnt
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* see valid HS and VS bits alternate) it
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* will generate lots of annoying beeps..
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*
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* So, the trick here is to just send it
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* some alternating bits, making it think
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* the CGA circuitry is operational.
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*/
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sigma->fake_stat ^= (0x08 | 0x01);
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result = sigma->fake_stat;
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}
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break;
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}
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return result;
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}
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static void
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sigma_write(uint32_t addr, uint8_t val, void *p)
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{
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sigma_t *sigma = (sigma_t *) p;
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sigma->vram[sigma->plane * 0x8000 + (addr & 0x7fff)] = val;
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cycles -= 4;
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}
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static uint8_t
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sigma_read(uint32_t addr, void *p)
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{
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sigma_t *sigma = (sigma_t *) p;
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cycles -= 4;
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return sigma->vram[sigma->plane * 0x8000 + (addr & 0x7fff)];
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}
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static void
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sigma_bwrite(uint32_t addr, uint8_t val, void *p)
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{
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sigma_t *sigma = (sigma_t *) p;
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addr &= 0x3FFF;
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if ((addr < 0x1800) || sigma->rom_paged || (addr >= 0x2000))
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;
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else
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sigma->bram[addr & 0x7FF] = val;
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}
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static uint8_t
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sigma_bread(uint32_t addr, void *p)
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{
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sigma_t *sigma = (sigma_t *) p;
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uint8_t result;
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addr &= 0x3FFF;
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if (addr >= 0x2000)
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return 0xFF;
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if (addr < 0x1800 || sigma->rom_paged)
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result = sigma->bios_rom.rom[addr & 0x1FFF];
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else
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result = sigma->bram[addr & 0x7FF];
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return result;
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}
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static void
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sigma_recalctimings(sigma_t *sigma)
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{
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double disptime;
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double _dispontime, _dispofftime;
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if (sigma->sigmamode & MODE_80COLS) {
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disptime = (sigma->crtc[0] + 1) << 1;
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_dispontime = (sigma->crtc[1]) << 1;
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} else {
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disptime = (sigma->crtc[0] + 1) << 2;
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_dispontime = sigma->crtc[1] << 2;
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}
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_dispofftime = disptime - _dispontime;
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_dispontime *= CGACONST;
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_dispofftime *= CGACONST;
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sigma->dispontime = (uint64_t) (_dispontime);
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sigma->dispofftime = (uint64_t) (_dispofftime);
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}
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/* Render a line in 80-column text mode */
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static void
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sigma_text80(sigma_t *sigma)
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{
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int x, c;
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uint8_t chr, attr;
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uint16_t ca = (sigma->crtc[15] | (sigma->crtc[14] << 8));
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uint16_t ma = ((sigma->ma & 0x3FFF) << 1);
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int drawcursor;
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uint32_t cols[4];
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uint8_t *vram = sigma->vram + (ma << 1);
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ca = ca << 1;
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if (sigma->sigma_ctl & CTL_CURSOR)
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++ca;
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ca &= 0x3fff;
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/* The Sigma 400 seems to use screen widths stated in words
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(40 for 80-column, 20 for 40-column) */
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for (x = 0; x < (sigma->crtc[1] << 1); x++) {
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chr = vram[x << 1];
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attr = vram[(x << 1) + 1];
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drawcursor = ((ma == ca) && sigma->con && sigma->cursoron);
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if (!(sigma->sigmamode & MODE_NOBLINK)) {
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cols[1] = (attr & 15) | 16;
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cols[0] = ((attr >> 4) & 7) | 16;
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if ((sigma->cgablink & 8) && (attr & 0x80) && !sigma->drawcursor)
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cols[1] = cols[0];
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} else { /* No blink */
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cols[1] = (attr & 15) | 16;
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cols[0] = (attr >> 4) | 16;
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}
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if (drawcursor) {
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for (c = 0; c < 8; c++) {
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if (sigma->sigmamode & MODE_FONT16)
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buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
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else
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buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdat[chr][sigma->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
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}
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} else {
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for (c = 0; c < 8; c++) {
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if (sigma->sigmamode & MODE_FONT16)
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buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
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else
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buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdat[chr][sigma->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
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}
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}
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++ma;
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}
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sigma->ma += sigma->crtc[1];
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}
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/* Render a line in 40-column text mode */
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static void
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sigma_text40(sigma_t *sigma)
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{
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int x, c;
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uint8_t chr, attr;
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uint16_t ca = (sigma->crtc[15] | (sigma->crtc[14] << 8));
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uint16_t ma = ((sigma->ma & 0x3FFF) << 1);
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int drawcursor;
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uint32_t cols[4];
|
|
uint8_t *vram = sigma->vram + ((ma << 1) & 0x3FFF);
|
|
|
|
ca = ca << 1;
|
|
if (sigma->sigma_ctl & CTL_CURSOR)
|
|
++ca;
|
|
ca &= 0x3fff;
|
|
|
|
/* The Sigma 400 seems to use screen widths stated in words
|
|
(40 for 80-column, 20 for 40-column) */
|
|
for (x = 0; x < (sigma->crtc[1] << 1); x++) {
|
|
chr = vram[x << 1];
|
|
attr = vram[(x << 1) + 1];
|
|
drawcursor = ((ma == ca) && sigma->con && sigma->cursoron);
|
|
|
|
if (!(sigma->sigmamode & MODE_NOBLINK)) {
|
|
cols[1] = (attr & 15) | 16;
|
|
cols[0] = ((attr >> 4) & 7) | 16;
|
|
if ((sigma->cgablink & 8) && (attr & 0x80) && !sigma->drawcursor)
|
|
cols[1] = cols[0];
|
|
} else { /* No blink */
|
|
cols[1] = (attr & 15) | 16;
|
|
cols[0] = (attr >> 4) | 16;
|
|
}
|
|
|
|
if (drawcursor) {
|
|
for (c = 0; c < 8; c++) {
|
|
buffer32->line[sigma->displine][(x << 4) + 2 * c + 8] = buffer32->line[sigma->displine][(x << 4) + 2 * c + 9] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
|
|
}
|
|
} else {
|
|
for (c = 0; c < 8; c++) {
|
|
buffer32->line[sigma->displine][(x << 4) + 2 * c + 8] = buffer32->line[sigma->displine][(x << 4) + 2 * c + 9] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
|
|
}
|
|
}
|
|
ma++;
|
|
}
|
|
|
|
sigma->ma += sigma->crtc[1];
|
|
}
|
|
|
|
/* Draw a line in the 640x400 graphics mode */
|
|
static void
|
|
sigma_gfx400(sigma_t *sigma)
|
|
{
|
|
int x;
|
|
unsigned char *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 3) * 0x2000];
|
|
uint8_t plane[4];
|
|
uint8_t mask, col, c;
|
|
|
|
for (x = 0; x < (sigma->crtc[1] << 1); x++) {
|
|
plane[0] = vram[x];
|
|
plane[1] = vram[0x8000 + x];
|
|
plane[2] = vram[0x10000 + x];
|
|
plane[3] = vram[0x18000 + x];
|
|
|
|
for (c = 0, mask = 0x80; c < 8; c++, mask >>= 1) {
|
|
col = ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0) | ((plane[1] & mask) ? 2 : 0) | ((plane[0] & mask) ? 1 : 0);
|
|
col |= 16;
|
|
buffer32->line[sigma->displine][(x << 3) + c + 8] = col;
|
|
}
|
|
if (x & 1)
|
|
++sigma->ma;
|
|
}
|
|
}
|
|
|
|
/* Draw a line in the 640x200 graphics mode.
|
|
* This is actually a 640x200x16 mode; on startup, the BIOS selects plane 2,
|
|
* blanks the other planes, and sets palette ink 4 to white. Pixels plotted
|
|
* in plane 2 come out in white, others black; but by programming the palette
|
|
* and plane registers manually you can get the full resolution. */
|
|
static void
|
|
sigma_gfx200(sigma_t *sigma)
|
|
{
|
|
int x;
|
|
unsigned char *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 2) * 0x1000];
|
|
uint8_t plane[4];
|
|
uint8_t mask, col, c;
|
|
|
|
for (x = 0; x < (sigma->crtc[1] << 1); x++) {
|
|
plane[0] = vram[x];
|
|
plane[1] = vram[0x8000 + x];
|
|
plane[2] = vram[0x10000 + x];
|
|
plane[3] = vram[0x18000 + x];
|
|
|
|
for (c = 0, mask = 0x80; c < 8; c++, mask >>= 1) {
|
|
col = ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0) | ((plane[1] & mask) ? 2 : 0) | ((plane[0] & mask) ? 1 : 0);
|
|
col |= 16;
|
|
buffer32->line[sigma->displine][(x << 3) + c + 8] = col;
|
|
}
|
|
|
|
if (x & 1)
|
|
++sigma->ma;
|
|
}
|
|
}
|
|
|
|
/* Draw a line in the 320x200 graphics mode */
|
|
static void
|
|
sigma_gfx4col(sigma_t *sigma)
|
|
{
|
|
int x;
|
|
unsigned char *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 2) * 0x1000];
|
|
uint8_t plane[4];
|
|
uint8_t mask, col, c;
|
|
|
|
for (x = 0; x < (sigma->crtc[1] << 1); x++) {
|
|
plane[0] = vram[x];
|
|
plane[1] = vram[0x8000 + x];
|
|
plane[2] = vram[0x10000 + x];
|
|
plane[3] = vram[0x18000 + x];
|
|
|
|
mask = 0x80;
|
|
for (c = 0; c < 4; c++) {
|
|
col = ((plane[3] & mask) ? 2 : 0) | ((plane[2] & mask) ? 1 : 0);
|
|
mask = mask >> 1;
|
|
col |= ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0);
|
|
col |= 16;
|
|
mask = mask >> 1;
|
|
|
|
buffer32->line[sigma->displine][(x << 3) + (c << 1) + 8] = buffer32->line[sigma->displine][(x << 3) + (c << 1) + 9] = col;
|
|
}
|
|
|
|
if (x & 1)
|
|
++sigma->ma;
|
|
}
|
|
}
|
|
|
|
static void
|
|
sigma_poll(void *p)
|
|
{
|
|
sigma_t *sigma = (sigma_t *) p;
|
|
int x, c;
|
|
int oldvc;
|
|
uint32_t cols[4];
|
|
int oldsc;
|
|
|
|
if (!sigma->linepos) {
|
|
timer_advance_u64(&sigma->timer, sigma->dispofftime);
|
|
sigma->sigmastat |= STATUS_RETR_H;
|
|
sigma->linepos = 1;
|
|
oldsc = sigma->sc;
|
|
if ((sigma->crtc[8] & 3) == 3)
|
|
sigma->sc = ((sigma->sc << 1) + sigma->oddeven) & 7;
|
|
if (sigma->cgadispon) {
|
|
if (sigma->displine < sigma->firstline) {
|
|
sigma->firstline = sigma->displine;
|
|
video_wait_for_buffer();
|
|
}
|
|
sigma->lastline = sigma->displine;
|
|
|
|
cols[0] = 16;
|
|
/* Left overscan */
|
|
for (c = 0; c < 8; c++) {
|
|
buffer32->line[sigma->displine][c] = cols[0];
|
|
if (sigma->sigmamode & MODE_80COLS)
|
|
buffer32->line[sigma->displine][c + (sigma->crtc[1] << 4) + 8] = cols[0];
|
|
else
|
|
buffer32->line[sigma->displine][c + (sigma->crtc[1] << 5) + 8] = cols[0];
|
|
}
|
|
if (sigma->sigmamode & MODE_GRAPHICS) {
|
|
if (sigma->sigmamode & MODE_640x400)
|
|
sigma_gfx400(sigma);
|
|
else if (sigma->sigmamode & MODE_HRGFX)
|
|
sigma_gfx200(sigma);
|
|
else
|
|
sigma_gfx4col(sigma);
|
|
} else { /* Text modes */
|
|
if (sigma->sigmamode & MODE_80COLS)
|
|
sigma_text80(sigma);
|
|
else
|
|
sigma_text40(sigma);
|
|
}
|
|
} else {
|
|
cols[0] = 16;
|
|
if (sigma->sigmamode & MODE_80COLS)
|
|
hline(buffer32, 0, sigma->displine, (sigma->crtc[1] << 4) + 16, cols[0]);
|
|
else
|
|
hline(buffer32, 0, sigma->displine, (sigma->crtc[1] << 5) + 16, cols[0]);
|
|
}
|
|
|
|
if (sigma->sigmamode & MODE_80COLS)
|
|
x = (sigma->crtc[1] << 4) + 16;
|
|
else
|
|
x = (sigma->crtc[1] << 5) + 16;
|
|
|
|
for (c = 0; c < x; c++)
|
|
buffer32->line[sigma->displine][c] = sigma->palette[buffer32->line[sigma->displine][c] & 0xf] | 16;
|
|
|
|
video_process_8(x, sigma->displine);
|
|
|
|
sigma->sc = oldsc;
|
|
if (sigma->vc == sigma->crtc[7] && !sigma->sc)
|
|
sigma->sigmastat |= STATUS_RETR_V;
|
|
sigma->displine++;
|
|
if (sigma->displine >= 560)
|
|
sigma->displine = 0;
|
|
} else {
|
|
timer_advance_u64(&sigma->timer, sigma->dispontime);
|
|
sigma->linepos = 0;
|
|
if (sigma->vsynctime) {
|
|
sigma->vsynctime--;
|
|
if (!sigma->vsynctime)
|
|
sigma->sigmastat &= ~STATUS_RETR_V;
|
|
}
|
|
if (sigma->sc == (sigma->crtc[11] & 31) || ((sigma->crtc[8] & 3) == 3 && sigma->sc == ((sigma->crtc[11] & 31) >> 1))) {
|
|
sigma->con = 0;
|
|
sigma->coff = 1;
|
|
}
|
|
if ((sigma->crtc[8] & 3) == 3 && sigma->sc == (sigma->crtc[9] >> 1))
|
|
sigma->maback = sigma->ma;
|
|
if (sigma->vadj) {
|
|
sigma->sc++;
|
|
sigma->sc &= 31;
|
|
sigma->ma = sigma->maback;
|
|
sigma->vadj--;
|
|
if (!sigma->vadj) {
|
|
sigma->cgadispon = 1;
|
|
sigma->ma = sigma->maback = (sigma->crtc[13] | (sigma->crtc[12] << 8)) & 0x3fff;
|
|
sigma->sc = 0;
|
|
}
|
|
} else if (sigma->sc == sigma->crtc[9]) {
|
|
sigma->maback = sigma->ma;
|
|
sigma->sc = 0;
|
|
oldvc = sigma->vc;
|
|
sigma->vc++;
|
|
sigma->vc &= 127;
|
|
|
|
if (sigma->vc == sigma->crtc[6])
|
|
sigma->cgadispon = 0;
|
|
|
|
if (oldvc == sigma->crtc[4]) {
|
|
sigma->vc = 0;
|
|
sigma->vadj = sigma->crtc[5];
|
|
if (!sigma->vadj)
|
|
sigma->cgadispon = 1;
|
|
if (!sigma->vadj)
|
|
sigma->ma = sigma->maback = (sigma->crtc[13] | (sigma->crtc[12] << 8)) & 0x3fff;
|
|
if ((sigma->crtc[10] & 0x60) == 0x20)
|
|
sigma->cursoron = 0;
|
|
else
|
|
sigma->cursoron = sigma->cgablink & 8;
|
|
}
|
|
|
|
if (sigma->vc == sigma->crtc[7]) {
|
|
sigma->cgadispon = 0;
|
|
sigma->displine = 0;
|
|
sigma->vsynctime = 16;
|
|
if (sigma->crtc[7]) {
|
|
if (sigma->sigmamode & MODE_80COLS)
|
|
x = (sigma->crtc[1] << 4) + 16;
|
|
else
|
|
x = (sigma->crtc[1] << 5) + 16;
|
|
sigma->lastline++;
|
|
if ((x != xsize) || ((sigma->lastline - sigma->firstline) != ysize) || video_force_resize_get()) {
|
|
xsize = x;
|
|
ysize = sigma->lastline - sigma->firstline;
|
|
if (xsize < 64)
|
|
xsize = 656;
|
|
if (ysize < 32)
|
|
ysize = 200;
|
|
if (ysize <= 250)
|
|
set_screen_size(xsize, (ysize << 1) + 16);
|
|
else
|
|
set_screen_size(xsize, ysize + 8);
|
|
|
|
if (video_force_resize_get())
|
|
video_force_resize_set(0);
|
|
}
|
|
|
|
video_blit_memtoscreen(0, sigma->firstline - 4, xsize, (sigma->lastline - sigma->firstline) + 8);
|
|
frames++;
|
|
|
|
video_res_x = xsize - 16;
|
|
video_res_y = ysize;
|
|
if (sigma->sigmamode & MODE_GRAPHICS) {
|
|
if (sigma->sigmamode & (MODE_HRGFX | MODE_640x400))
|
|
video_bpp = 1;
|
|
else {
|
|
video_res_x /= 2;
|
|
video_bpp = 2;
|
|
}
|
|
} else if (sigma->sigmamode & MODE_80COLS) {
|
|
/* 80-column text */
|
|
video_res_x /= 8;
|
|
video_res_y /= sigma->crtc[9] + 1;
|
|
video_bpp = 0;
|
|
} else {
|
|
/* 40-column text */
|
|
video_res_x /= 16;
|
|
video_res_y /= sigma->crtc[9] + 1;
|
|
video_bpp = 0;
|
|
}
|
|
}
|
|
sigma->firstline = 1000;
|
|
sigma->lastline = 0;
|
|
sigma->cgablink++;
|
|
sigma->oddeven ^= 1;
|
|
}
|
|
} else {
|
|
sigma->sc++;
|
|
sigma->sc &= 31;
|
|
sigma->ma = sigma->maback;
|
|
}
|
|
if (sigma->cgadispon)
|
|
sigma->sigmastat &= ~STATUS_RETR_H;
|
|
if ((sigma->sc == (sigma->crtc[10] & 31) || ((sigma->crtc[8] & 3) == 3 && sigma->sc == ((sigma->crtc[10] & 31) >> 1))))
|
|
sigma->con = 1;
|
|
}
|
|
}
|
|
|
|
static void
|
|
*
|
|
sigma_init(const device_t *info)
|
|
{
|
|
int bios_addr;
|
|
sigma_t *sigma = malloc(sizeof(sigma_t));
|
|
memset(sigma, 0, sizeof(sigma_t));
|
|
|
|
bios_addr = device_get_config_hex20("bios_addr");
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_sigma);
|
|
|
|
sigma->enable_nmi = device_get_config_int("enable_nmi");
|
|
|
|
loadfont(ROM_SIGMA_FONT, 7);
|
|
rom_init(&sigma->bios_rom, ROM_SIGMA_BIOS, bios_addr, 0x2000,
|
|
0x1FFF, 0, MEM_MAPPING_EXTERNAL);
|
|
/* The BIOS ROM is overlaid by RAM, so remove its default mapping
|
|
and access it through sigma_bread() / sigma_bwrite() below */
|
|
mem_mapping_disable(&sigma->bios_rom.mapping);
|
|
memcpy(sigma->bram, &sigma->bios_rom.rom[0x1800], 0x800);
|
|
|
|
sigma->vram = malloc(0x8000 * 4);
|
|
|
|
timer_add(&sigma->timer, sigma_poll, sigma, 1);
|
|
mem_mapping_add(&sigma->mapping, 0xb8000, 0x08000,
|
|
sigma_read, NULL, NULL,
|
|
sigma_write, NULL, NULL,
|
|
NULL, MEM_MAPPING_EXTERNAL, sigma);
|
|
mem_mapping_add(&sigma->bios_ram, bios_addr, 0x2000,
|
|
sigma_bread, NULL, NULL,
|
|
sigma_bwrite, NULL, NULL,
|
|
sigma->bios_rom.rom, MEM_MAPPING_EXTERNAL, sigma);
|
|
io_sethandler(0x03d0, 0x0010,
|
|
sigma_in, NULL, NULL,
|
|
sigma_out, NULL, NULL, sigma);
|
|
io_sethandler(0x02d0, 0x0010,
|
|
sigma_in, NULL, NULL,
|
|
sigma_out, NULL, NULL, sigma);
|
|
|
|
/* Start with ROM paged in, BIOS RAM paged out */
|
|
sigma->rom_paged = 0x80;
|
|
|
|
cga_palette = device_get_config_int("rgb_type") << 1;
|
|
if (cga_palette > 6)
|
|
cga_palette = 0;
|
|
cgapal_rebuild();
|
|
|
|
if (sigma->enable_nmi)
|
|
sigma->sigmastat = STATUS_LPEN_T;
|
|
|
|
return sigma;
|
|
}
|
|
|
|
static int
|
|
sigma_available(void)
|
|
{
|
|
return ((rom_present(ROM_SIGMA_FONT) && rom_present(ROM_SIGMA_BIOS)));
|
|
}
|
|
|
|
static void
|
|
sigma_close(void *p)
|
|
{
|
|
sigma_t *sigma = (sigma_t *) p;
|
|
|
|
free(sigma->vram);
|
|
free(sigma);
|
|
}
|
|
|
|
void
|
|
sigma_speed_changed(void *p)
|
|
{
|
|
sigma_t *sigma = (sigma_t *) p;
|
|
|
|
sigma_recalctimings(sigma);
|
|
}
|
|
|
|
device_config_t sigma_config[] = {
|
|
// clang-format off
|
|
{
|
|
.name = "rgb_type",
|
|
.description = "RGB type",
|
|
.type = CONFIG_SELECTION,
|
|
.default_int = 0,
|
|
.selection = {
|
|
{
|
|
.description = "Color",
|
|
.value = 0
|
|
},
|
|
{
|
|
.description = "Green Monochrome",
|
|
.value = 1
|
|
},
|
|
{
|
|
.description = "Amber Monochrome",
|
|
.value = 2
|
|
},
|
|
{
|
|
.description = "Gray Monochrome",
|
|
.value = 3
|
|
},
|
|
{
|
|
.description = "Color (no brown)",
|
|
.value = 4
|
|
},
|
|
{
|
|
.description = ""
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.name = "enable_nmi",
|
|
.description = "Enable NMI for CGA emulation",
|
|
.type = CONFIG_BINARY,
|
|
.default_int = 1
|
|
},
|
|
{
|
|
.name = "bios_addr",
|
|
.description = "BIOS Address",
|
|
.type = CONFIG_HEX20,
|
|
.default_int = 0xc0000,
|
|
.selection = {
|
|
{
|
|
.description = "C000H",
|
|
.value = 0xc0000
|
|
},
|
|
{
|
|
.description = "C800H",
|
|
.value = 0xc8000
|
|
},
|
|
{
|
|
.description = "CC00H",
|
|
.value = 0xcc000
|
|
},
|
|
{
|
|
.description = "D000H",
|
|
.value = 0xd0000
|
|
},
|
|
{
|
|
.description = "D400H",
|
|
.value = 0xd4000
|
|
},
|
|
{
|
|
.description = "D800H",
|
|
.value = 0xd8000
|
|
},
|
|
{
|
|
.description = "DC00H",
|
|
.value = 0xdc000
|
|
},
|
|
{
|
|
.description = "E000H",
|
|
.value = 0xe0000
|
|
},
|
|
{
|
|
.description = "E400H",
|
|
.value = 0xe4000
|
|
},
|
|
{
|
|
.description = "E800H",
|
|
.value = 0xe8000
|
|
},
|
|
{
|
|
.description = "EC00H",
|
|
.value = 0xec000
|
|
},
|
|
{
|
|
.description = ""
|
|
}
|
|
},
|
|
},
|
|
{
|
|
.type = CONFIG_END
|
|
}
|
|
// clang-format on
|
|
};
|
|
|
|
const device_t sigma_device = {
|
|
.name = "Sigma Color 400",
|
|
.internal_name = "sigma400",
|
|
.flags = DEVICE_ISA,
|
|
.local = 0,
|
|
.init = sigma_init,
|
|
.close = sigma_close,
|
|
.reset = NULL,
|
|
{ .available = sigma_available },
|
|
.speed_changed = sigma_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = sigma_config
|
|
};
|