55b6f1b802
Floppy disk controller is now COMPLETELY reset on hard reset; NukedOPL is now optional (but enabled by default) so people on older hardware can gain a few % of performance by going back to DOSBox OPL; *.CPP files now get all the correct optimization flags applied; Added NEC PowerMate V emulation - you can get into CMOS SETUP but it hangs before booting, and PCI graphics card don't work (yet).
185 lines
3.4 KiB
C
185 lines
3.4 KiB
C
/* Copyright holders: Tenshi
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see COPYING for more details
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*/
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/*PRD format :
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word 0 - base address
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word 1 - bits 1 - 15 = byte count, bit 31 = end of transfer
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*/
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#include <string.h>
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#include "ibm.h"
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#include "cdrom.h"
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#include "cpu.h"
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#include "ide.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "sio.h"
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static uint8_t card_sio[256];
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void sio_write(int func, int addr, uint8_t val, void *priv)
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{
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// pclog("sio_write: func=%d addr=%02x val=%02x %04x:%08x\n", func, addr, val, CS, pc);
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if ((addr & 0xff) < 4) return;
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if (func > 0)
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return;
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if (func == 0)
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{
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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}
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card_sio[addr] = val;
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if (addr == 0x40)
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{
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if (!((val ^ card_sio[addr]) & 0x40))
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{
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return;
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}
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if (val & 0x40)
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{
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dma_alias_remove();
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}
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else
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{
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dma_alias_set();
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}
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}
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else if (addr == 0x4f)
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{
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if (!((val ^ card_sio[addr]) & 0x40))
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{
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return;
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}
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if (val & 0x40)
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{
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port_92_add();
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}
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else
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{
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port_92_remove();
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}
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}
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}
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}
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uint8_t sio_read(int func, int addr, void *priv)
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{
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// pclog("sio_read: func=%d addr=%02x %04x:%08x\n", func, addr, CS, pc);
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if (func > 0)
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return 0xff;
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return card_sio[addr];
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}
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static int trc_reg = 0;
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uint8_t trc_read(uint16_t port, void *priv)
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{
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return trc_reg & 0xfb;
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}
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void trc_write(uint16_t port, uint8_t val, void *priv)
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{
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int i = 0;
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pclog("TRC Write: %02X\n", val);
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if (!(trc_reg & 4) && (val & 4))
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{
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if (val & 2)
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{
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if (pci_reset_handler.pci_master_reset)
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{
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pci_reset_handler.pci_master_reset();
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}
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if (pci_reset_handler.pci_set_reset)
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{
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pci_reset_handler.pci_set_reset();
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}
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fdc_hard_reset();
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if (pci_reset_handler.super_io_reset)
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{
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pci_reset_handler.super_io_reset();
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}
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resetide();
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for (i = 0; i < CDROM_NUM; i++)
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{
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if (!cdrom_drives[i].bus_type)
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{
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cdrom_reset(i);
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}
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}
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port_92_reset();
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keyboard_at_reset();
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}
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resetx86();
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}
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trc_reg = val & 0xfd;
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}
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void trc_init()
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{
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trc_reg = 0;
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io_sethandler(0x0cf9, 0x0001, trc_read, NULL, NULL, trc_write, NULL, NULL, NULL);
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}
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void sio_reset(void)
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{
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memset(card_sio, 0, 256);
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card_sio[0x00] = 0x86; card_sio[0x01] = 0x80; /*Intel*/
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card_sio[0x02] = 0x84; card_sio[0x03] = 0x04; /*82378ZB (SIO)*/
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card_sio[0x04] = 0x07; card_sio[0x05] = 0x00;
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card_sio[0x06] = 0x00; card_sio[0x07] = 0x02;
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card_sio[0x08] = 0x00; /*A0 stepping*/
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card_sio[0x40] = 0x20;
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card_sio[0x42] = 0x24;
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card_sio[0x45] = 0x10;
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card_sio[0x46] = 0x0F;
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card_sio[0x48] = 0x01;
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card_sio[0x4A] = 0x10;
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card_sio[0x4B] = 0x0F;
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card_sio[0x4C] = 0x56;
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card_sio[0x4D] = 0x40;
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card_sio[0x4E] = 0x07;
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card_sio[0x4F] = 0x4F;
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card_sio[0x60] = card_sio[0x61] = card_sio[0x62] = card_sio[0x63] = 0x80;
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card_sio[0x80] = 0x78;
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card_sio[0xA0] = 0x08;
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card_sio[0xA8] = 0x0F;
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}
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void sio_init(int card)
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{
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pci_add_specific(card, sio_read, sio_write, NULL);
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sio_reset();
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trc_init();
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port_92_reset();
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port_92_add();
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dma_alias_set();
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pci_reset_handler.pci_set_reset = sio_reset;
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}
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