632 lines
22 KiB
C
632 lines
22 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the NCR 5380 chip made by NCR
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* and used in various controllers.
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*
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*
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*
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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* TheCollector1995, <mariogplayer@gmail.com>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2017-2019 Sarah Walker.
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* Copyright 2017-2019 Fred N. van Kempen.
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* Copyright 2017-2024 TheCollector1995.
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/dma.h>
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#include <86box/pic.h>
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#include <86box/mca.h>
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#include <86box/mem.h>
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#include <86box/rom.h>
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#include <86box/device.h>
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#include <86box/nvr.h>
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#include <86box/plat.h>
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#include <86box/scsi.h>
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#include <86box/scsi_device.h>
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#include <86box/scsi_ncr5380.h>
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int ncr5380_cmd_len[8] = { 6, 10, 10, 6, 16, 12, 10, 6 };
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#ifdef ENABLE_NCR5380_LOG
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int ncr5380_do_log = ENABLE_NCR5380_LOG;
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static void
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ncr5380_log(const char *fmt, ...)
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{
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va_list ap;
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if (ncr5380_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define ncr5380_log(fmt, ...)
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#endif
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#define SET_BUS_STATE(ncr, state) ncr->cur_bus = (ncr->cur_bus & ~(SCSI_PHASE_MESSAGE_IN)) | (state & (SCSI_PHASE_MESSAGE_IN))
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void
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ncr5380_irq(ncr_t *ncr, int set_irq)
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{
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if (set_irq) {
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ncr->irq_state = 1;
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ncr->isr |= STATUS_INT;
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if (ncr->irq != -1)
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picint(1 << ncr->irq);
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} else {
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ncr->irq_state = 0;
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ncr->isr &= ~STATUS_INT;
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if (ncr->irq != 1)
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picintc(1 << ncr->irq);
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}
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}
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void
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ncr5380_set_irq(ncr_t *ncr, int irq)
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{
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ncr->irq = irq;
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}
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static int
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ncr5380_get_dev_id(uint8_t data)
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{
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for (uint8_t c = 0; c < SCSI_ID_MAX; c++) {
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if (data & (1 << c))
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return c;
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}
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return -1;
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}
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static int
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ncr5380_getmsglen(uint8_t *msgp, int len)
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{
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uint8_t msg = msgp[0];
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if (msg == 0 || (msg >= 0x02 && msg <= 0x1f) || msg >= 0x80)
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return 1;
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if (msg >= 0x20 && msg <= 0x2f)
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return 2;
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if (len < 2)
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return 3;
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return msgp[1];
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}
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static void
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ncr5380_reset(ncr_t *ncr)
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{
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ncr->command_pos = 0;
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ncr->data_pos = 0;
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ncr->state = STATE_IDLE;
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ncr->clear_req = 0;
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ncr->cur_bus = 0;
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ncr->tx_data = 0;
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ncr->output_data = 0;
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ncr->data_wait = 0;
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ncr->mode = 0;
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ncr->tcr = 0;
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ncr->icr = 0;
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ncr->dma_mode = DMA_IDLE;
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ncr5380_log("NCR Reset\n");
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ncr->timer(ncr->priv, 0.0);
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for (int i = 0; i < 8; i++)
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scsi_device_reset(&scsi_devices[ncr->bus][i]);
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ncr5380_irq(ncr, 0);
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}
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uint32_t
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ncr5380_get_bus_host(ncr_t *ncr)
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{
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uint32_t bus_host = 0;
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if (ncr->icr & ICR_DBP)
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bus_host |= BUS_DBP;
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if (ncr->icr & ICR_SEL)
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bus_host |= BUS_SEL;
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if (ncr->tcr & TCR_IO)
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bus_host |= BUS_IO;
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if (ncr->tcr & TCR_CD)
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bus_host |= BUS_CD;
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if (ncr->tcr & TCR_MSG)
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bus_host |= BUS_MSG;
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if (ncr->tcr & TCR_REQ)
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bus_host |= BUS_REQ;
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if (ncr->icr & ICR_BSY)
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bus_host |= BUS_BSY;
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if (ncr->icr & ICR_ATN)
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bus_host |= BUS_ATN;
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if (ncr->icr & ICR_ACK)
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bus_host |= BUS_ACK;
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if (ncr->mode & MODE_ARBITRATE)
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bus_host |= BUS_ARB;
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return (bus_host | BUS_SETDATA(ncr->output_data));
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}
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void
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ncr5380_bus_read(ncr_t *ncr)
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{
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const scsi_device_t *dev;
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int phase;
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/*Wait processes to handle bus requests*/
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if (ncr->clear_req) {
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ncr->clear_req--;
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if (!ncr->clear_req) {
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ncr5380_log("Prelude to command data\n");
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SET_BUS_STATE(ncr, ncr->new_phase);
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ncr->cur_bus |= BUS_REQ;
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}
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}
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if (ncr->wait_data) {
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ncr->wait_data--;
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if (!ncr->wait_data) {
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dev = &scsi_devices[ncr->bus][ncr->target_id];
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SET_BUS_STATE(ncr, ncr->new_phase);
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phase = (ncr->cur_bus & SCSI_PHASE_MESSAGE_IN);
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if (phase == SCSI_PHASE_DATA_IN) {
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if ((ncr->dma_mode == DMA_IDLE) || ncr->dma_initiator_receive_ext || (ncr->wait_data_back == 1)) {
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ncr5380_log("Phase Data In.\n");
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if ((dev->sc != NULL) && (dev->sc->temp_buffer != NULL))
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ncr->tx_data = dev->sc->temp_buffer[ncr->data_pos++];
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ncr->state = STATE_DATAIN;
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ncr->cur_bus = (ncr->cur_bus & ~BUS_DATAMASK) | BUS_SETDATA(ncr->tx_data) | BUS_DBP;
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}
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} else if (phase == SCSI_PHASE_DATA_OUT) {
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if (ncr->new_phase & BUS_IDLE) {
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ncr->state = STATE_IDLE;
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ncr->cur_bus &= ~BUS_BSY;
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} else {
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if ((ncr->dma_mode == DMA_IDLE) || ncr->dma_send_ext || (ncr->wait_data_back == 1))
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ncr->state = STATE_DATAOUT;
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}
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} else if (phase == SCSI_PHASE_STATUS) {
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ncr5380_log("Phase Status.\n");
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ncr->wait_data_back = 0;
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ncr->cur_bus |= BUS_REQ;
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ncr->state = STATE_STATUS;
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ncr->cur_bus = (ncr->cur_bus & ~BUS_DATAMASK) | BUS_SETDATA(dev->status) | BUS_DBP;
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} else if (phase == SCSI_PHASE_MESSAGE_IN) {
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ncr5380_log("Phase Message In.\n");
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ncr->state = STATE_MESSAGEIN;
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ncr->cur_bus = (ncr->cur_bus & ~BUS_DATAMASK) | BUS_SETDATA(0) | BUS_DBP;
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} else if (phase == SCSI_PHASE_MESSAGE_OUT) {
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ncr->cur_bus |= BUS_REQ;
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ncr->state = STATE_MESSAGEOUT;
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ncr->cur_bus = (ncr->cur_bus & ~BUS_DATAMASK) | BUS_SETDATA(ncr->target_id >> 5) | BUS_DBP;
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}
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}
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}
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if (ncr->wait_complete) {
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ncr->wait_complete--;
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if (!ncr->wait_complete)
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ncr->cur_bus |= BUS_REQ;
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}
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}
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void
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ncr5380_bus_update(ncr_t *ncr, int bus)
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{
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scsi_device_t *dev = &scsi_devices[ncr->bus][ncr->target_id];
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double p;
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uint8_t sel_data;
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int msglen;
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/*Start the SCSI command layer, which will also make the timings*/
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if (bus & BUS_ARB)
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ncr->state = STATE_IDLE;
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ncr5380_log("State = %i\n", ncr->state);
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switch (ncr->state) {
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case STATE_IDLE:
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ncr->clear_req = ncr->wait_data = ncr->wait_complete = 0;
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if ((bus & BUS_SEL) && !(bus & BUS_BSY)) {
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ncr5380_log("Selection phase\n");
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sel_data = BUS_GETDATA(bus);
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ncr->target_id = ncr5380_get_dev_id(sel_data);
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ncr5380_log("Select - target ID = %i\n", ncr->target_id);
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/*Once the device has been found and selected, mark it as busy*/
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if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr->bus][ncr->target_id])) {
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ncr->cur_bus |= BUS_BSY;
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ncr->state = STATE_SELECT;
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} else {
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ncr5380_log("Device not found at ID %i, Current Bus BSY=%02x\n", ncr->target_id, ncr->cur_bus);
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ncr->cur_bus = 0;
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}
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}
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break;
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case STATE_SELECT:
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if (!(bus & BUS_SEL)) {
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if (!(bus & BUS_ATN)) {
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if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr->bus][ncr->target_id])) {
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ncr5380_log("Device found at ID %i, Current Bus BSY=%02x\n", ncr->target_id, ncr->cur_bus);
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ncr->state = STATE_COMMAND;
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ncr->cur_bus = BUS_BSY | BUS_REQ;
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ncr5380_log("CurBus BSY|REQ=%02x\n", ncr->cur_bus);
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ncr->command_pos = 0;
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SET_BUS_STATE(ncr, SCSI_PHASE_COMMAND);
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} else {
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ncr->state = STATE_IDLE;
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ncr->cur_bus = 0;
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}
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} else {
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ncr5380_log("Set to SCSI Message Out\n");
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ncr->new_phase = SCSI_PHASE_MESSAGE_OUT;
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ncr->wait_data = 4;
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ncr->msgout_pos = 0;
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ncr->is_msgout = 1;
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}
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}
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break;
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case STATE_COMMAND:
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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/*Write command byte to the output data register*/
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ncr->command[ncr->command_pos++] = BUS_GETDATA(bus);
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ncr->clear_req = 3;
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ncr->new_phase = ncr->cur_bus & SCSI_PHASE_MESSAGE_IN;
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ncr->cur_bus &= ~BUS_REQ;
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ncr5380_log("Command pos=%i, output data=%02x\n", ncr->command_pos, BUS_GETDATA(bus));
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if (ncr->command_pos == ncr5380_cmd_len[(ncr->command[0] >> 5) & 7]) {
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if (ncr->is_msgout) {
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ncr->is_msgout = 0;
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#if 0
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ncr->command[1] = (ncr->command[1] & 0x1f) | (ncr->msglun << 5);
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#endif
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}
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/*Reset data position to default*/
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ncr->data_pos = 0;
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dev = &scsi_devices[ncr->bus][ncr->target_id];
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ncr5380_log("SCSI Command 0x%02X for ID %d, status code=%02x\n", ncr->command[0], ncr->target_id, dev->status);
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dev->buffer_length = -1;
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scsi_device_command_phase0(dev, ncr->command);
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ncr5380_log("SCSI ID %i: Command %02X: Buffer Length %i, SCSI Phase %02X\n", ncr->target_id, ncr->command[0], dev->buffer_length, dev->phase);
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ncr->period = 1.0;
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ncr->wait_data = 4;
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ncr->data_wait = 0;
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if (dev->status == SCSI_STATUS_OK) {
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/*If the SCSI phase is Data In or Data Out, allocate the SCSI buffer based on the transfer length of the command*/
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if (dev->buffer_length && ((dev->phase == SCSI_PHASE_DATA_IN) || (dev->phase == SCSI_PHASE_DATA_OUT))) {
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p = scsi_device_get_callback(dev);
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ncr->period = (p > 0.0) ? p : (((double) dev->buffer_length) * 0.2);
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ncr5380_log("SCSI ID %i: command 0x%02x for p = %lf, update = %lf, len = %i, dmamode = %x\n", ncr->target_id, ncr->command[0], scsi_device_get_callback(dev), ncr->period, dev->buffer_length, ncr->dma_mode);
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}
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}
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ncr->new_phase = dev->phase;
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}
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}
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break;
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case STATE_DATAIN:
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dev = &scsi_devices[ncr->bus][ncr->target_id];
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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if (ncr->data_pos >= dev->buffer_length) {
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ncr->cur_bus &= ~BUS_REQ;
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ncr5380_log("CMD Phase1 DataIn.\n");
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scsi_device_command_phase1(dev);
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ncr->new_phase = SCSI_PHASE_STATUS;
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ncr->wait_data = 4;
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ncr->wait_complete = 8;
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} else {
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if ((dev->sc != NULL) && (dev->sc->temp_buffer != NULL))
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ncr->tx_data = dev->sc->temp_buffer[ncr->data_pos++];
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ncr->cur_bus = (ncr->cur_bus & ~BUS_DATAMASK) | BUS_SETDATA(ncr->tx_data) | BUS_DBP | BUS_REQ;
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if (ncr->dma_mode == DMA_IDLE) { /*If a data in command that is not read 6/10 has been issued*/
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ncr->data_wait |= 1;
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ncr5380_log("DMA mode idle IN=%d.\n", ncr->data_pos);
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ncr->timer(ncr->priv, ncr->period);
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} else {
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ncr5380_log("DMA mode IN=%d.\n", ncr->data_pos);
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ncr->clear_req = 3;
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}
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ncr->cur_bus &= ~BUS_REQ;
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ncr->new_phase = SCSI_PHASE_DATA_IN;
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}
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}
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break;
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case STATE_DATAOUT:
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dev = &scsi_devices[ncr->bus][ncr->target_id];
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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if ((dev->sc != NULL) && (dev->sc->temp_buffer != NULL))
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dev->sc->temp_buffer[ncr->data_pos++] = BUS_GETDATA(bus);
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if (ncr->data_pos >= dev->buffer_length) {
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ncr->cur_bus &= ~BUS_REQ;
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scsi_device_command_phase1(dev);
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ncr->new_phase = SCSI_PHASE_STATUS;
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ncr->wait_data = 4;
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ncr->wait_complete = 8;
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} else {
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/*More data is to be transferred, place a request*/
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if (ncr->dma_mode == DMA_IDLE) { /*If a data out command that is not write 6/10 has been issued*/
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ncr->data_wait |= 1;
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ncr5380_log("DMA mode idle out\n");
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ncr->timer(ncr->priv, ncr->period);
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} else
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ncr->clear_req = 3;
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ncr->cur_bus &= ~BUS_REQ;
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ncr5380_log("CurBus ~REQ_DataOut=%02x\n", ncr->cur_bus);
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}
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}
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break;
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case STATE_STATUS:
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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/*All transfers done, wait until next transfer*/
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scsi_device_identify(&scsi_devices[ncr->bus][ncr->target_id], SCSI_LUN_USE_CDB);
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ncr->cur_bus &= ~BUS_REQ;
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ncr->new_phase = SCSI_PHASE_MESSAGE_IN;
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ncr->wait_data = 4;
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ncr->wait_complete = 8;
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}
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break;
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case STATE_MESSAGEIN:
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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ncr->cur_bus &= ~BUS_REQ;
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ncr->new_phase = BUS_IDLE;
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ncr->wait_data = 4;
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}
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break;
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case STATE_MESSAGEOUT:
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ncr5380_log("Ack on MSGOUT = %02x\n", (bus & BUS_ACK));
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if ((bus & BUS_ACK) && !(ncr->bus_in & BUS_ACK)) {
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ncr->msgout[ncr->msgout_pos++] = BUS_GETDATA(bus);
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msglen = ncr5380_getmsglen(ncr->msgout, ncr->msgout_pos);
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if (ncr->msgout_pos >= msglen) {
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if ((ncr->msgout[0] & (0x80 | 0x20)) == 0x80)
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ncr->msglun = ncr->msgout[0] & 7;
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ncr->cur_bus &= ~BUS_REQ;
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ncr->state = STATE_MESSAGE_ID;
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}
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}
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break;
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case STATE_MESSAGE_ID:
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if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr->bus][ncr->target_id])) {
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ncr5380_log("Device found at ID %i on MSGOUT, Current Bus BSY=%02x\n", ncr->target_id, ncr->cur_bus);
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scsi_device_identify(&scsi_devices[ncr->bus][ncr->target_id], ncr->msglun);
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ncr->state = STATE_COMMAND;
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ncr->cur_bus = BUS_BSY | BUS_REQ;
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ncr5380_log("CurBus BSY|REQ=%02x\n", ncr->cur_bus);
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ncr->command_pos = 0;
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SET_BUS_STATE(ncr, SCSI_PHASE_COMMAND);
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}
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break;
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default:
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break;
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}
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ncr->bus_in = bus;
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}
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void
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ncr5380_write(uint16_t port, uint8_t val, ncr_t *ncr)
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{
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int bus_host = 0;
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ncr5380_log("NCR5380 write(%04x,%02x)\n", port & 7, val);
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switch (port & 7) {
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case 0: /* Output data register */
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ncr5380_log("[%04X:%08X]: Write: Output data register, val=%02x\n", CS, cpu_state.pc, val);
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ncr->output_data = val;
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break;
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case 1: /* Initiator Command Register */
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ncr5380_log("[%04X:%08X]: Write: Initiator command register, val=%02x.\n", CS, cpu_state.pc, val);
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if ((val & 0x80) && !(ncr->icr & 0x80)) {
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ncr5380_log("Resetting the 5380\n");
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ncr5380_reset(ncr);
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}
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ncr->icr = val;
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break;
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case 2: /* Mode register */
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ncr5380_log("Write: Mode register, val=%02x.\n", val);
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if ((val & MODE_ARBITRATE) && !(ncr->mode & MODE_ARBITRATE)) {
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ncr->icr &= ~ICR_ARB_LOST;
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ncr->icr |= ICR_ARB_IN_PROGRESS;
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}
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ncr->mode = val;
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ncr->dma_mode_ext(ncr, ncr->priv);
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break;
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case 3: /* Target Command Register */
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ncr5380_log("Write: Target Command register, val=%02x.\n", val);
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ncr->tcr = val;
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break;
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case 4: /* Select Enable Register */
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ncr5380_log("Write: Select Enable register\n");
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break;
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case 5: /* start DMA Send */
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ncr5380_log("Write: start DMA send register\n");
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/*a Write 6/10 has occurred, start the timer when the block count is loaded*/
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ncr->dma_mode = DMA_SEND;
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if (ncr->dma_send_ext)
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ncr->dma_send_ext(ncr, ncr->priv);
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break;
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case 7: /* start DMA Initiator Receive */
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ncr5380_log("[%04X:%08X]: Write: start DMA initiator receive register, dma? = %02x\n", CS, cpu_state.pc, ncr->mode & MODE_DMA);
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/*a Read 6/10 has occurred, start the timer when the block count is loaded*/
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ncr->dma_mode = DMA_INITIATOR_RECEIVE;
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if (ncr->dma_initiator_receive_ext)
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ncr->dma_initiator_receive_ext(ncr, ncr->priv);
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break;
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default:
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ncr5380_log("NCR5380: bad write %04x %02x\n", port, val);
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break;
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}
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bus_host = ncr5380_get_bus_host(ncr);
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ncr5380_bus_update(ncr, bus_host);
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}
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uint8_t
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ncr5380_read(uint16_t port, ncr_t *ncr)
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{
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uint8_t ret = 0xff;
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int bus;
|
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int bus_state;
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|
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switch (port & 7) {
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case 0: /* Current SCSI data */
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ncr5380_log("Read: Current SCSI data register\n");
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if (ncr->icr & ICR_DBP) {
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/*Return the data from the output register if on data bus phase from ICR*/
|
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ret = ncr->output_data;
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ncr5380_log("[%04X:%08X]: Data Bus Phase, ret=%02x, clearreq=%d, waitdata=%x.\n", CS, cpu_state.pc, ret, ncr->clear_req, ncr->wait_data);
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} else {
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/*Return the data from the SCSI bus*/
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ncr5380_bus_read(ncr);
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ret = BUS_GETDATA(ncr->cur_bus);
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ncr5380_log("[%04X:%08X]: NCR Get SCSI bus data=%02x.\n", CS, cpu_state.pc, ret);
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}
|
|
break;
|
|
|
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case 1: /* Initiator Command Register */
|
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ncr5380_log("Read: Initiator Command register, NCR ICR Read=%02x\n", ncr->icr);
|
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ret = ncr->icr;
|
|
break;
|
|
|
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case 2: /* Mode register */
|
|
ncr5380_log("Read: Mode register = %02x.\n", ncr->mode);
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ret = ncr->mode;
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break;
|
|
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case 3: /* Target Command Register */
|
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ncr5380_log("Read: Target Command register, NCR target stat=%02x\n", ncr->tcr);
|
|
ret = ncr->tcr;
|
|
break;
|
|
|
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case 4: /* Current SCSI Bus status */
|
|
ncr5380_log("Read: SCSI bus status register\n");
|
|
ret = 0;
|
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ncr5380_bus_read(ncr);
|
|
ncr5380_log("NCR cur bus stat=%02x\n", ncr->cur_bus & 0xff);
|
|
ret |= (ncr->cur_bus & 0xff);
|
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if (ncr->icr & ICR_SEL)
|
|
ret |= BUS_SEL;
|
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if (ncr->icr & ICR_BSY)
|
|
ret |= BUS_BSY;
|
|
// if ((ret & SCSI_PHASE_MESSAGE_IN) == SCSI_PHASE_MESSAGE_IN)
|
|
// ret &= ~BUS_REQ;
|
|
break;
|
|
|
|
case 5: /* Bus and Status register */
|
|
ncr5380_log("Read: Bus and Status register\n");
|
|
ret = 0;
|
|
|
|
bus = ncr5380_get_bus_host(ncr);
|
|
ncr5380_log("Get host from Interrupt\n");
|
|
|
|
/*Check if the phase in process matches with TCR's*/
|
|
if ((bus & SCSI_PHASE_MESSAGE_IN) == (ncr->cur_bus & SCSI_PHASE_MESSAGE_IN)) {
|
|
ncr5380_log("Phase match\n");
|
|
ret |= STATUS_PHASE_MATCH;
|
|
}
|
|
|
|
ncr5380_bus_read(ncr);
|
|
bus = ncr->cur_bus;
|
|
|
|
if ((bus & BUS_ACK) || (ncr->icr & ICR_ACK))
|
|
ret |= STATUS_ACK;
|
|
if ((bus & BUS_ATN) || (ncr->icr & ICR_ATN))
|
|
ret |= 0x02;
|
|
|
|
if ((bus & BUS_REQ) && (ncr->mode & MODE_DMA)) {
|
|
ncr5380_log("Entering DMA mode\n");
|
|
ret |= STATUS_DRQ;
|
|
|
|
bus_state = 0;
|
|
|
|
if (bus & BUS_IO)
|
|
bus_state |= TCR_IO;
|
|
if (bus & BUS_CD)
|
|
bus_state |= TCR_CD;
|
|
if (bus & BUS_MSG)
|
|
bus_state |= TCR_MSG;
|
|
if ((ncr->tcr & 7) != bus_state) {
|
|
ncr5380_irq(ncr, 1);
|
|
ncr5380_log("IRQ issued\n");
|
|
}
|
|
}
|
|
if (!(bus & BUS_BSY) && (ncr->mode & MODE_MONITOR_BUSY)) {
|
|
ncr5380_log("Busy error\n");
|
|
ret |= STATUS_BUSY_ERROR;
|
|
}
|
|
ret |= (ncr->isr & (STATUS_INT | STATUS_END_OF_DMA));
|
|
break;
|
|
|
|
case 6:
|
|
ncr5380_log("Read: Input Data.\n");
|
|
ncr5380_bus_read(ncr);
|
|
ret = BUS_GETDATA(ncr->cur_bus);
|
|
break;
|
|
|
|
case 7: /* reset Parity/Interrupt */
|
|
ncr->isr &= ~(STATUS_BUSY_ERROR | 0x20);
|
|
ncr5380_irq(ncr, 0);
|
|
ncr5380_log("Reset Interrupt\n");
|
|
break;
|
|
|
|
default:
|
|
ncr5380_log("NCR5380: bad read %04x\n", port);
|
|
break;
|
|
}
|
|
|
|
ncr5380_log("NCR5380 read(%04x)=%02x\n", port & 7, ret);
|
|
|
|
return ret;
|
|
}
|