394 lines
7.7 KiB
C
394 lines
7.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of Intel System I/O PCI chip.
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*
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* Version: @(#)intel_sio.c 1.0.9 2018/10/02
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2018 Sarah Walker.
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* Copyright 2016-2018 Miran Grca.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "device.h"
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#include "io.h"
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#include "apm.h"
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#include "dma.h"
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#include "mem.h"
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#include "pci.h"
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#include "timer.h"
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#include "pit.h"
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#include "port_92.h"
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#include "machine/machine.h"
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#include "intel_sio.h"
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typedef struct
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{
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uint8_t id,
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regs[256];
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uint16_t timer_base,
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timer_latch;
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pc_timer_t timer;
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port_92_t * port_92;
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} sio_t;
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static void
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sio_timer_write(uint16_t addr, uint8_t val, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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if (!(addr & 0x0002)) {
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if (addr & 0x0001)
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dev->timer_latch = (dev->timer_latch & 0xff) | (val << 8);
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else
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dev->timer_latch = (dev->timer_latch & 0xff00) | val;
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timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
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}
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}
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static void
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sio_timer_writew(uint16_t addr, uint16_t val, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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if (!(addr & 0x0002)) {
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dev->timer_latch = val;
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timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
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}
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}
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static uint8_t
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sio_timer_read(uint16_t addr, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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uint16_t sio_timer_latch;
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uint8_t ret = 0xff;
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if (!(addr & 0x0002)) {
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sub_cycles((int)(PITCONST >> 32));
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sio_timer_latch = timer_get_remaining_us(&dev->timer);
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if (addr & 0x0001)
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ret = sio_timer_latch >> 8;
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else
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ret = sio_timer_latch & 0xff;
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}
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return ret;
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}
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static uint16_t
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sio_timer_readw(uint16_t addr, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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uint16_t ret = 0xffff;
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if (!(addr & 0x0002)) {
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sub_cycles((int)(PITCONST >> 32));
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ret = timer_get_remaining_us(&dev->timer);
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}
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return ret;
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}
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static void
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sio_write(int func, int addr, uint8_t val, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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uint8_t old;
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if (func > 0)
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return;
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if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40))
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return;
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/* The IB (original) variant of the SIO has no PCI IRQ steering. */
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if ((addr >= 0x60) && (addr <= 0x63) && (dev->id < 0x03))
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return;
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old = dev->regs[addr];
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dev->regs[addr] = val;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x04: /*Command register*/
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val &= 0x08;
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val |= 0x07;
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break;
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case 0x05:
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val = 0;
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break;
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case 0x06: /*Status*/
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val = 0;
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break;
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case 0x07:
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val = 0x02;
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break;
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case 0x40:
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if (!((val ^ old) & 0x40))
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return;
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dma_alias_remove();
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if (val & 0x40)
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dma_alias_set();
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break;
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case 0x4f:
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if (!((val ^ old) & 0x40))
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return;
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port_92_remove(dev->port_92);
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if (val & 0x40)
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port_92_add(dev->port_92);
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break;
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case 0x60:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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break;
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case 0x61:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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break;
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case 0x62:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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break;
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case 0x63:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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break;
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case 0x80:
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case 0x81:
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if (dev->timer_base & 0x01) {
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io_removehandler(dev->timer_base & 0xfffc, 0x0004,
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sio_timer_read, sio_timer_readw, NULL,
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sio_timer_write, sio_timer_writew, NULL, dev);
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}
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dev->timer_base = (dev->regs[0x81] << 8) | (dev->regs[0x80] & 0xfd);
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if (dev->timer_base & 0x01) {
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io_sethandler(dev->timer_base & 0xfffc, 0x0004,
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sio_timer_read, sio_timer_readw, NULL,
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sio_timer_write, sio_timer_writew, NULL, dev);
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}
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break;
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}
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}
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static uint8_t
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sio_read(int func, int addr, void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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uint8_t ret;
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ret = 0xff;
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if (func == 0)
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ret = dev->regs[addr];
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return ret;
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}
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static void
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sio_config_write(uint16_t addr, uint8_t val, void *priv)
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{
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}
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static uint8_t
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sio_config_read(uint16_t port, void *priv)
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{
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uint8_t ret = 0x00;
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switch (port & 0x000f) {
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case 3:
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ret = 0xff;
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break;
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case 5:
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ret = 0xd3;
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switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].pci_speed) {
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case 20000000:
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ret |= 0x0c;
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break;
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case 25000000:
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default:
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ret |= 0x00;
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break;
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case 30000000:
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ret |= 0x08;
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break;
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case 33333333:
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ret |= 0x04;
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break;
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}
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break;
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}
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return ret;
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}
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static void
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sio_reset(void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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memset(dev->regs, 0, 256);
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dev->regs[0x00] = 0x86; dev->regs[0x01] = 0x80; /*Intel*/
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dev->regs[0x02] = 0x84; dev->regs[0x03] = 0x04; /*82378IB (SIO)*/
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dev->regs[0x04] = 0x07; dev->regs[0x05] = 0x00;
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dev->regs[0x06] = 0x00; dev->regs[0x07] = 0x02;
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dev->regs[0x08] = dev->id;
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dev->regs[0x40] = 0x20; dev->regs[0x41] = 0x00;
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dev->regs[0x42] = 0x04; dev->regs[0x43] = 0x00;
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dev->regs[0x44] = 0x20; dev->regs[0x45] = 0x10;
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dev->regs[0x46] = 0x0f; dev->regs[0x47] = 0x00;
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dev->regs[0x48] = 0x01; dev->regs[0x49] = 0x10;
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dev->regs[0x4a] = 0x10; dev->regs[0x4b] = 0x0f;
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dev->regs[0x4c] = 0x56; dev->regs[0x4d] = 0x40;
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dev->regs[0x4e] = 0x07; dev->regs[0x4f] = 0x4f;
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dev->regs[0x54] = 0x00; dev->regs[0x55] = 0x00; dev->regs[0x56] = 0x00;
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dev->regs[0x60] = 0x80; dev->regs[0x61] = 0x80; dev->regs[0x62] = 0x80; dev->regs[0x63] = 0x80;
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dev->regs[0x80] = 0x78; dev->regs[0x81] = 0x00;
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dev->regs[0xa0] = 0x08;
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dev->regs[0xa8] = 0x0f;
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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if (dev->timer_base & 0x0001) {
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io_removehandler(dev->timer_base & 0xfffc, 0x0004,
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sio_timer_read, sio_timer_readw, NULL,
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sio_timer_write, sio_timer_writew, NULL, dev);
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}
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dev->timer_base = 0x0078;
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}
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static void
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sio_close(void *p)
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{
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sio_t *sio = (sio_t *)p;
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free(sio);
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}
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static void
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sio_speed_changed(void *priv)
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{
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sio_t *dev = (sio_t *) priv;
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int te;
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te = timer_is_enabled(&dev->timer);
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timer_disable(&dev->timer);
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if (te)
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timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
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}
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static void *
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sio_init(const device_t *info)
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{
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sio_t *sio = (sio_t *) malloc(sizeof(sio_t));
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memset(sio, 0, sizeof(sio_t));
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pci_add_card(2, sio_read, sio_write, sio);
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device_add(&apm_device);
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sio->id = info->local;
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sio_reset(sio);
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sio->port_92 = device_add(&port_92_pci_device);
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dma_alias_set();
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io_sethandler(0x0073, 0x0001,
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sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, sio);
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io_sethandler(0x0075, 0x0001,
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sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, sio);
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timer_add(&sio->timer, NULL, NULL, 0);
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return sio;
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}
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const device_t sio_device =
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{
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"Intel 82378IB (SIO)",
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DEVICE_PCI,
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0x00,
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sio_init,
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sio_close,
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NULL,
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NULL,
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sio_speed_changed,
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NULL,
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NULL
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};
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const device_t sio_zb_device =
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{
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"Intel 82378ZB (SIO)",
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DEVICE_PCI,
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0x03,
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sio_init,
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sio_close,
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NULL,
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NULL,
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sio_speed_changed,
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NULL,
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NULL
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};
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