407 lines
9.9 KiB
C
407 lines
9.9 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of a generic PIIX4-compatible SMBus host controller.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/timer.h>
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#include <86box/i2c.h>
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#include <86box/smbus.h>
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#ifdef ENABLE_SMBUS_PIIX4_LOG
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int smbus_piix4_do_log = ENABLE_SMBUS_PIIX4_LOG;
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static void
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smbus_piix4_log(const char *fmt, ...)
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{
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va_list ap;
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if (smbus_piix4_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define smbus_piix4_log(fmt, ...)
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#endif
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static uint8_t
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smbus_piix4_read(uint16_t addr, void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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uint8_t ret = 0x00;
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switch (addr - dev->io_base) {
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case 0x00:
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ret = dev->stat;
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break;
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case 0x02:
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dev->index = 0; /* reading from this resets the block data index */
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ret = dev->ctl;
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break;
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case 0x03:
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ret = dev->cmd;
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break;
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case 0x04:
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ret = dev->addr;
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break;
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case 0x05:
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ret = dev->data0;
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break;
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case 0x06:
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ret = dev->data1;
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break;
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case 0x07:
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ret = dev->data[dev->index++];
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if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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}
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smbus_piix4_log("SMBus PIIX4: read(%02X) = %02x\n", addr, ret);
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return ret;
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}
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static void
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smbus_piix4_write(uint16_t addr, uint8_t val, void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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uint8_t smbus_addr, cmd, read, block_len, prev_stat;
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uint16_t timer_bytes = 0, i;
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smbus_piix4_log("SMBus PIIX4: write(%02X, %02X)\n", addr, val);
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prev_stat = dev->next_stat;
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dev->next_stat = 0x00;
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switch (addr - dev->io_base) {
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case 0x00:
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for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr <<= 1) { /* handle clearable bits */
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if (val & smbus_addr)
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dev->stat &= ~smbus_addr;
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}
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break;
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case 0x02:
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dev->ctl = val & ((dev->local == SMBUS_VIA) ? 0x3f : 0x1f);
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if (val & 0x02) { /* cancel an in-progress command if KILL is set */
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if (prev_stat) { /* cancel only if a command is in progress */
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timer_disable(&dev->response_timer);
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dev->stat = 0x10; /* raise FAILED */
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}
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}
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if (val & 0x40) { /* dispatch command if START is set */
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timer_bytes++; /* address */
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smbus_addr = dev->addr >> 1;
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read = dev->addr & 0x01;
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cmd = (dev->ctl >> 2) & 0xf;
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smbus_piix4_log("SMBus PIIX4: addr=%02X read=%d protocol=%X cmd=%02X data0=%02X data1=%02X\n", smbus_addr, read, cmd, dev->cmd, dev->data0, dev->data1);
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/* Raise DEV_ERR if no device is at this address, or if the device returned NAK. */
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if (!i2c_start(i2c_smbus, smbus_addr, read)) {
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dev->next_stat = 0x04;
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break;
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}
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dev->next_stat = 0x02; /* raise INTER (command completed) by default */
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/* Decode the command protocol.
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VIA-specific modes (0x4 and [0x6:0xf]) are undocumented and required real hardware research. */
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switch (cmd) {
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case 0x0: /* quick R/W */
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break;
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case 0x1: /* byte R/W */
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if (read) /* byte read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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timer_bytes++;
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break;
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case 0x2: /* byte data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) /* byte read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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timer_bytes++;
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break;
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case 0x3: /* word data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) { /* word read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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dev->data1 = i2c_read(i2c_smbus, smbus_addr);
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} else { /* word write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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i2c_write(i2c_smbus, smbus_addr, dev->data1);
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}
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timer_bytes += 2;
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break;
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case 0x4: /* process call */
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if (dev->local != SMBUS_VIA) /* VIA only */
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goto unknown_protocol;
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if (!read) { /* command write (only when writing) */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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}
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/* fall-through */
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case 0xc: /* I2C process call */
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if (!read) { /* word write (only when writing) */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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i2c_write(i2c_smbus, smbus_addr, dev->data1);
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timer_bytes += 2;
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}
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/* word read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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dev->data1 = i2c_read(i2c_smbus, smbus_addr);
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timer_bytes += 2;
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break;
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case 0x5: /* block R/W */
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timer_bytes++; /* count the SMBus length byte now */
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/* fall-through */
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case 0xd: /* I2C block R/W */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) {
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/* block read [data0] (I2C) or [first byte] (SMBus) bytes */
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if (cmd == 0x5)
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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for (i = 0; i < dev->data0; i++)
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dev->data[i & SMBUS_PIIX4_BLOCK_DATA_MASK] = i2c_read(i2c_smbus, smbus_addr);
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} else {
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if (cmd == 0x5) /* send length [data0] as first byte on SMBus */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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/* block write [data0] bytes */
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for (i = 0; i < dev->data0; i++) {
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if (!i2c_write(i2c_smbus, smbus_addr, dev->data[i & SMBUS_PIIX4_BLOCK_DATA_MASK]))
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break;
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}
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}
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timer_bytes += i;
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break;
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case 0x6: /* I2C with 10-bit address */
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if (dev->local != SMBUS_VIA) /* VIA only */
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goto unknown_protocol;
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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/* fall-through */
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case 0xe: /* I2C with 7-bit address */
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if (!read) { /* word write (only when writing) */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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i2c_write(i2c_smbus, smbus_addr, dev->data1);
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timer_bytes += 2;
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}
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/* block read [first byte] bytes */
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block_len = dev->data[0];
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for (i = 0; i < block_len; i++)
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dev->data[i & SMBUS_PIIX4_BLOCK_DATA_MASK] = i2c_read(i2c_smbus, smbus_addr);
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timer_bytes += i;
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break;
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case 0xf: /* universal */
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/* block write [data0] bytes */
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for (i = 0; i < dev->data0; i++) {
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if (!i2c_write(i2c_smbus, smbus_addr, dev->data[i & SMBUS_PIIX4_BLOCK_DATA_MASK]))
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break; /* write NAK behavior is unknown */
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}
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timer_bytes += i;
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/* block read [data1] bytes */
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for (i = 0; i < dev->data1; i++)
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dev->data[i & SMBUS_PIIX4_BLOCK_DATA_MASK] = i2c_read(i2c_smbus, smbus_addr);
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timer_bytes += i;
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break;
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default: /* unknown */
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unknown_protocol:
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dev->next_stat = 0x04; /* raise DEV_ERR */
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timer_bytes = 0;
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break;
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}
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/* Finish transfer. */
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i2c_stop(i2c_smbus, smbus_addr);
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}
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break;
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case 0x03:
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dev->cmd = val;
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break;
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case 0x04:
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dev->addr = val;
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break;
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case 0x05:
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dev->data0 = val;
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break;
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case 0x06:
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dev->data1 = val;
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break;
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case 0x07:
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dev->data[dev->index++] = val;
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if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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}
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if (dev->next_stat) { /* schedule dispatch of any pending status register update */
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dev->stat = 0x01; /* raise HOST_BUSY while waiting */
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timer_disable(&dev->response_timer);
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/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * bit period in usecs */
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timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * dev->bit_period * TIMER_USEC);
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}
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}
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static void
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smbus_piix4_response(void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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/* Dispatch the status register update. */
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dev->stat = dev->next_stat;
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}
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void
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smbus_piix4_remap(smbus_piix4_t *dev, uint16_t new_io_base, uint8_t enable)
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{
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if (dev->io_base)
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io_removehandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev);
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dev->io_base = new_io_base;
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smbus_piix4_log("SMBus PIIX4: remap to %04Xh (%sabled)\n", dev->io_base, enable ? "en" : "dis");
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if (enable && dev->io_base)
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io_sethandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev);
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}
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void
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smbus_piix4_setclock(smbus_piix4_t *dev, int clock)
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{
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dev->clock = clock;
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/* Set the bit period in usecs. */
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dev->bit_period = 1000000.0 / dev->clock;
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}
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static void *
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smbus_piix4_init(const device_t *info)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) malloc(sizeof(smbus_piix4_t));
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memset(dev, 0, sizeof(smbus_piix4_t));
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dev->local = info->local;
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/* We save the I2C bus handle on dev but use i2c_smbus for all operations because
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dev and therefore dev->i2c will be invalidated if a device triggers a hard reset. */
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i2c_smbus = dev->i2c = i2c_addbus((dev->local == SMBUS_VIA) ? "smbus_vt82c686b" : "smbus_piix4");
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timer_add(&dev->response_timer, smbus_piix4_response, dev, 0);
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smbus_piix4_setclock(dev, 16384); /* default to 16.384 KHz */
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return dev;
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}
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static void
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smbus_piix4_close(void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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if (i2c_smbus == dev->i2c)
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i2c_smbus = NULL;
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i2c_removebus(dev->i2c);
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free(dev);
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}
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const device_t piix4_smbus_device = {
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"PIIX4-compatible SMBus Host Controller",
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"piix4_smbus",
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DEVICE_AT,
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SMBUS_PIIX4,
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smbus_piix4_init, smbus_piix4_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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const device_t via_smbus_device = {
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"VIA VT82C686B SMBus Host Controller",
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"via_smbus",
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DEVICE_AT,
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SMBUS_VIA,
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smbus_piix4_init, smbus_piix4_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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