5318bc08d8
Merged floppy.c and fdd.c and renamed floppy_*.c (the floppy image format handlers) to fdd_*.c; Reading the AT or PS/2 keyboard controller status no longer clears the transmit timeout bit, fixes error 8601 (mouse error) on the IBM PS/2 Model 80; MMU translate and DMA physical reads and writes now go through _mem_exec instead of directly to ram[], should fix the last remaining problems with remapped mappings; Implemented the Sound gain dialog; Added the resource for the "New floppy image" dialog and the needed functions for the functionality of exporting the currently mounted floppy image as 86F, both of which should be finished in the next commit; Applied the CD-ROM fixes from the PCem commit; Added the "Keep ratio" option for full screen stretch.
580 lines
13 KiB
C
580 lines
13 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SMC FDC37C932FR and FDC37C935 Super
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* I/O Chips.
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*
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* Version: @(#)sio_fdc37c93x.c 1.0.10 2018/01/16
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*
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* Author: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2016-2018 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "io.h"
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#include "device.h"
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#include "pci.h"
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#include "lpt.h"
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#include "serial.h"
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#include "disk/hdc.h"
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#include "disk/hdc_ide.h"
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#include "floppy/fdd.h"
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#include "floppy/fdc.h"
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#include "sio.h"
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static int fdc37c93x_locked;
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static int fdc37c93x_curreg = 0;
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static int fdc37c93x_gpio_reg = 0;
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static uint8_t fdc37c93x_regs[48];
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static uint8_t fdc37c93x_ld_regs[10][256];
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static uint8_t fdc37c93x_gpio_base = 0x00EA;
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static fdc_t *fdc37c93x_fdc;
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static uint8_t tries;
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static uint16_t make_port(uint8_t ld)
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{
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uint16_t r0 = fdc37c93x_ld_regs[ld][0x60];
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uint16_t r1 = fdc37c93x_ld_regs[ld][0x61];
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uint16_t p = (r0 << 8) + r1;
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return p;
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}
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static uint8_t fdc37c93x_gpio_read(uint16_t port, void *priv)
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{
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/* pclog("fdc37c93x: GPIO read: %02X\n", fdc37c93x_gpio_reg); */
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return fdc37c93x_gpio_reg;
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}
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static void fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv)
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{
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/* pclog("fdc37c93x: GPIO write: %02X\n", val); */
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fdc37c93x_gpio_reg = val;
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}
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static void fdc37c93x_fdc_handler(void)
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{
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uint16_t ld_port = 0;
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uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 0));
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uint8_t local_enable = !!fdc37c93x_ld_regs[0][0x30];
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fdc_remove(fdc37c93x_fdc);
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/* pclog("fdc37c93x: Removing FDC (%i, %i)\n", global_enable, local_enable); */
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if (global_enable && local_enable)
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{
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ld_port = make_port(0);
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/* pclog("fdc37c93x: Setting FDC port to %04X\n", ld_port); */
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8)) {
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fdc_set_base(fdc37c93x_fdc, ld_port);
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}
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}
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}
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static void fdc37c93x_lpt_handler(void)
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{
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uint16_t ld_port = 0;
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uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 3));
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uint8_t local_enable = !!fdc37c93x_ld_regs[3][0x30];
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lpt1_remove();
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if (global_enable && local_enable)
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{
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ld_port = make_port(3);
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/* pclog("fdc37c93x: Setting LPT1 port to %04X\n", ld_port); */
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
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lpt1_init(ld_port);
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}
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}
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static void fdc37c93x_serial_handler(int uart)
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{
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uint16_t ld_port = 0;
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uint8_t uart_no = 3 + uart;
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uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << uart_no));
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uint8_t local_enable = !!fdc37c93x_ld_regs[uart_no][0x30];
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serial_remove(uart);
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if (global_enable && local_enable)
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{
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ld_port = make_port(uart_no);
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/* pclog("fdc37c93x: Setting COM%i port to %04X\n", uart, ld_port); */
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
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serial_setup(uart, ld_port, fdc37c93x_ld_regs[uart_no][0x70]);
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}
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}
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static void fdc37c93x_auxio_handler(void)
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{
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uint16_t ld_port = 0;
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uint8_t local_enable = !!fdc37c93x_ld_regs[3][0x30];
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io_removehandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
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if (local_enable)
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{
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fdc37c93x_gpio_base = ld_port = make_port(3);
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/* pclog("fdc37c93x: Setting Auxiliary I/O port to %04X\n", ld_port); */
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
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io_sethandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
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}
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}
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#define AB_RST 0x80
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typedef struct {
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uint8_t control;
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uint8_t status;
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uint8_t own_addr;
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uint8_t data;
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uint8_t clock;
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uint16_t base;
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} access_bus_t;
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static access_bus_t access_bus;
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static uint8_t fdc37c932fr_access_bus_read(uint16_t port, void *priv)
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{
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switch(port & 3) {
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case 0:
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return (access_bus.status & 0xBF);
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break;
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case 1:
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return (access_bus.own_addr & 0x7F);
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break;
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case 2:
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return access_bus.data;
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break;
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case 3:
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return (access_bus.clock & 0x87);
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break;
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default:
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return 0xFF;
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}
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}
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static void fdc37c932fr_access_bus_write(uint16_t port, uint8_t val, void *priv)
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{
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switch(port & 3) {
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case 0:
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access_bus.control = (val & 0xCF);
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break;
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case 1:
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access_bus.own_addr = (val & 0x7F);
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break;
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case 2:
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access_bus.data = val;
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break;
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case 3:
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access_bus.clock &= 0x80;
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access_bus.clock |= (val & 0x07);
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break;
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}
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}
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static void fdc37c932fr_access_bus_handler(void)
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{
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uint16_t ld_port = 0;
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uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 6));
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uint8_t local_enable = !!fdc37c93x_ld_regs[9][0x30];
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io_removehandler(access_bus.base, 0x0004, fdc37c932fr_access_bus_read, NULL, NULL, fdc37c932fr_access_bus_write, NULL, NULL, NULL);
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if (global_enable && local_enable)
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{
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access_bus.base = ld_port = make_port(9);
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/* pclog("fdc37c93x: Setting Auxiliary I/O port to %04X\n", ld_port); */
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
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io_sethandler(access_bus.base, 0x0004, fdc37c932fr_access_bus_read, NULL, NULL, fdc37c932fr_access_bus_write, NULL, NULL, NULL);
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}
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}
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static void fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
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{
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t valxor = 0;
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if (index)
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{
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if ((val == 0x55) && !fdc37c93x_locked)
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{
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if (tries)
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{
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fdc37c93x_locked = 1;
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fdc_3f1_enable(fdc37c93x_fdc, 0);
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tries = 0;
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}
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else
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{
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tries++;
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}
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}
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else
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{
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if (fdc37c93x_locked)
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{
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if (val == 0xaa)
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{
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fdc37c93x_locked = 0;
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fdc_3f1_enable(fdc37c93x_fdc, 1);
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return;
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}
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fdc37c93x_curreg = val;
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}
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else
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{
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if (tries)
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tries = 0;
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}
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}
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}
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else
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{
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if (fdc37c93x_locked)
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{
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if (fdc37c93x_curreg < 48)
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{
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valxor = val ^ fdc37c93x_regs[fdc37c93x_curreg];
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if ((val == 0x20) || (val == 0x21))
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return;
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fdc37c93x_regs[fdc37c93x_curreg] = val;
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goto process_value;
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}
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else
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{
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valxor = val ^ fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg];
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if (((fdc37c93x_curreg & 0xF0) == 0x70) && (fdc37c93x_regs[7] < 4)) return;
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/* Block writes to IDE configuration. */
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if (fdc37c93x_regs[7] == 1) return;
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if (fdc37c93x_regs[7] == 2) return;
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if ((fdc37c93x_regs[7] > 5) && (fdc37c93x_regs[7] != 8) && (fdc37c93x_regs[7] != 9)) return;
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if ((fdc37c93x_regs[7] == 9) && (fdc37c93x_regs[0x20] != 3)) return;
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fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg] = val;
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goto process_value;
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}
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}
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}
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return;
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process_value:
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if (fdc37c93x_curreg < 48)
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{
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switch(fdc37c93x_curreg)
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{
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case 0x22:
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if (valxor & 0x01)
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fdc37c93x_fdc_handler();
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if (valxor & 0x08)
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fdc37c93x_lpt_handler();
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if (valxor & 0x10)
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fdc37c93x_serial_handler(1);
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if (valxor & 0x20)
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fdc37c93x_serial_handler(2);
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break;
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}
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return;
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}
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switch(fdc37c93x_regs[7])
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{
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case 0:
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/* FDD */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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if (valxor)
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{
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fdc37c93x_fdc_handler();
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}
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break;
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case 0xF0:
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if (valxor & 0x01) fdc_update_enh_mode(fdc37c93x_fdc, val & 0x01);
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if (valxor & 0x10) fdc_set_swap(fdc37c93x_fdc, (val & 0x10) >> 4);
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break;
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case 0xF1:
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if (valxor & 0xC) fdc_update_densel_force(fdc37c93x_fdc, (val & 0xC) >> 2);
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break;
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case 0xF2:
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if (valxor & 0xC0) fdc_update_rwc(fdc37c93x_fdc, 3, (valxor & 0xC0) >> 6);
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if (valxor & 0x30) fdc_update_rwc(fdc37c93x_fdc, 2, (valxor & 0x30) >> 4);
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if (valxor & 0x0C) fdc_update_rwc(fdc37c93x_fdc, 1, (valxor & 0x0C) >> 2);
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if (valxor & 0x03) fdc_update_rwc(fdc37c93x_fdc, 0, (valxor & 0x03));
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break;
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case 0xF4:
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if (valxor & 0x18) fdc_update_drvrate(fdc37c93x_fdc, 0, (val & 0x18) >> 3);
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break;
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case 0xF5:
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if (valxor & 0x18) fdc_update_drvrate(fdc37c93x_fdc, 1, (val & 0x18) >> 3);
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break;
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case 0xF6:
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if (valxor & 0x18) fdc_update_drvrate(fdc37c93x_fdc, 2, (val & 0x18) >> 3);
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break;
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case 0xF7:
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if (valxor & 0x18) fdc_update_drvrate(fdc37c93x_fdc, 3, (val & 0x18) >> 3);
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break;
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}
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break;
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case 3:
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/* Parallel port */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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if (valxor)
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{
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fdc37c93x_lpt_handler();
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}
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break;
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}
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break;
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case 4:
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/* Serial port 1 */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor)
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{
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fdc37c93x_serial_handler(1);
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}
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break;
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}
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break;
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case 5:
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/* Serial port 2 */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor)
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{
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fdc37c93x_serial_handler(2);
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}
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break;
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}
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break;
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case 8:
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/* Serial port 2 */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor)
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{
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fdc37c93x_auxio_handler();
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}
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break;
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}
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break;
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case 9:
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/* Access bus (FDC37C932FR only) */
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switch(fdc37c93x_curreg)
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{
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor)
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{
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fdc37c932fr_access_bus_handler();
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}
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break;
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}
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break;
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}
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}
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static uint8_t fdc37c93x_read(uint16_t port, void *priv)
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{
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uint8_t index = (port & 1) ? 0 : 1;
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if (!fdc37c93x_locked)
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{
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return 0xff;
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}
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if (index)
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return fdc37c93x_curreg;
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else
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{
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if (fdc37c93x_curreg < 0x30)
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{
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return fdc37c93x_regs[fdc37c93x_curreg];
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}
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else
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{
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if ((fdc37c93x_regs[7] == 0) && (fdc37c93x_curreg == 0xF2)) return (fdc_get_rwc(fdc37c93x_fdc, 0) | (fdc_get_rwc(fdc37c93x_fdc, 1) << 2));
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return fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg];
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}
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}
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}
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static void fdc37c93x_reset(void)
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{
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int i = 0;
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memset(fdc37c93x_regs, 0, 48);
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fdc37c93x_regs[0x03] = 3;
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fdc37c93x_regs[0x21] = 1;
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fdc37c93x_regs[0x22] = 0x39;
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fdc37c93x_regs[0x24] = 4;
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fdc37c93x_regs[0x26] = 0xF0;
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fdc37c93x_regs[0x27] = 3;
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for (i = 0; i < 10; i++)
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{
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memset(fdc37c93x_ld_regs[i], 0, 256);
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}
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/* Logical device 0: FDD */
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fdc37c93x_ld_regs[0][0x30] = 1;
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fdc37c93x_ld_regs[0][0x60] = 3;
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fdc37c93x_ld_regs[0][0x61] = 0xF0;
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fdc37c93x_ld_regs[0][0x70] = 6;
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fdc37c93x_ld_regs[0][0x74] = 2;
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fdc37c93x_ld_regs[0][0xF0] = 0xE;
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fdc37c93x_ld_regs[0][0xF2] = 0xFF;
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/* Logical device 1: IDE1 */
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fdc37c93x_ld_regs[1][0x30] = 0;
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fdc37c93x_ld_regs[1][0x60] = 1;
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fdc37c93x_ld_regs[1][0x61] = 0xF0;
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fdc37c93x_ld_regs[1][0x62] = 3;
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fdc37c93x_ld_regs[1][0x63] = 0xF6;
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fdc37c93x_ld_regs[1][0x70] = 0xE;
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fdc37c93x_ld_regs[1][0xF0] = 0xC;
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|
|
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/* Logical device 2: IDE2 */
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fdc37c93x_ld_regs[2][0x30] = 0;
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fdc37c93x_ld_regs[2][0x60] = 1;
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fdc37c93x_ld_regs[2][0x61] = 0x70;
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fdc37c93x_ld_regs[2][0x62] = 3;
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fdc37c93x_ld_regs[2][0x63] = 0x76;
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fdc37c93x_ld_regs[2][0x70] = 0xF;
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|
|
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/* Logical device 3: Parallel Port */
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fdc37c93x_ld_regs[3][0x30] = 1;
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fdc37c93x_ld_regs[3][0x60] = 3;
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fdc37c93x_ld_regs[3][0x61] = 0x78;
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fdc37c93x_ld_regs[3][0x70] = 7;
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fdc37c93x_ld_regs[3][0x74] = 4;
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fdc37c93x_ld_regs[3][0xF0] = 0x3C;
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|
|
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/* Logical device 4: Serial Port 1 */
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fdc37c93x_ld_regs[4][0x30] = 1;
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fdc37c93x_ld_regs[4][0x60] = 3;
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fdc37c93x_ld_regs[4][0x61] = 0xf8;
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fdc37c93x_ld_regs[4][0x70] = 4;
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fdc37c93x_ld_regs[4][0xF0] = 3;
|
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serial_setup(1, 0x3f8, fdc37c93x_ld_regs[4][0x70]);
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|
|
|
/* Logical device 5: Serial Port 2 */
|
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fdc37c93x_ld_regs[5][0x30] = 1;
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fdc37c93x_ld_regs[5][0x60] = 2;
|
|
fdc37c93x_ld_regs[5][0x61] = 0xf8;
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fdc37c93x_ld_regs[5][0x70] = 3;
|
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fdc37c93x_ld_regs[5][0x74] = 4;
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fdc37c93x_ld_regs[5][0xF1] = 2;
|
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fdc37c93x_ld_regs[5][0xF2] = 3;
|
|
serial_setup(2, 0x2f8, fdc37c93x_ld_regs[5][0x70]);
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|
|
|
/* Logical device 6: RTC */
|
|
fdc37c93x_ld_regs[6][0x63] = 0x70;
|
|
fdc37c93x_ld_regs[6][0xF4] = 3;
|
|
|
|
/* Logical device 7: Keyboard */
|
|
fdc37c93x_ld_regs[7][0x30] = 1;
|
|
fdc37c93x_ld_regs[7][0x61] = 0x60;
|
|
fdc37c93x_ld_regs[7][0x70] = 1;
|
|
|
|
/* Logical device 8: Auxiliary I/O */
|
|
fdc37c93x_ld_regs[8][0x30] = 1;
|
|
fdc37c93x_ld_regs[8][0x61] = 0xEA;
|
|
|
|
/* Logical device 8: AUX I/O */
|
|
|
|
/* Logical device 9: ACCESS.bus */
|
|
|
|
io_removehandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
|
|
fdc37c93x_gpio_base = 0x00EA;
|
|
io_sethandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
|
|
|
|
fdc37c93x_lpt_handler();
|
|
fdc37c93x_serial_handler(1);
|
|
fdc37c93x_serial_handler(2);
|
|
fdc37c93x_auxio_handler();
|
|
|
|
fdc_reset(fdc37c93x_fdc);
|
|
|
|
fdc37c93x_locked = 0;
|
|
}
|
|
|
|
static void fdc37c932fr_reset(void)
|
|
{
|
|
fdc37c93x_reset();
|
|
|
|
fdc37c93x_regs[0x20] = 3;
|
|
|
|
fdc37c932fr_access_bus_handler();
|
|
}
|
|
|
|
static void fdc37c935_reset(void)
|
|
{
|
|
fdc37c93x_reset();
|
|
|
|
fdc37c93x_regs[0x20] = 2;
|
|
}
|
|
|
|
static void fdc37c93x_init(void)
|
|
{
|
|
lpt2_remove();
|
|
|
|
fdc37c93x_fdc = device_add(&fdc_at_smc_device);
|
|
|
|
fdc37c93x_gpio_reg = 0xFD;
|
|
|
|
io_sethandler(0x3f0, 0x0002, fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, NULL);
|
|
}
|
|
|
|
void fdc37c932fr_init(void)
|
|
{
|
|
fdc37c93x_init();
|
|
fdc37c932fr_reset();
|
|
|
|
pci_reset_handler.super_io_reset = fdc37c932fr_reset;
|
|
}
|
|
|
|
void fdc37c935_init(void)
|
|
{
|
|
fdc37c93x_init();
|
|
fdc37c935_reset();
|
|
|
|
pci_reset_handler.super_io_reset = fdc37c935_reset;
|
|
}
|