51bbebbfa3
- Disabled the 'is486' flag and moved them to 386 timings - Disabled cache on startup, enable-able later - RapidCAD fixes (permanently disable L1, correct EDX reset)
209 lines
7.0 KiB
C
209 lines
7.0 KiB
C
static int opCMPXCHG_b_a16(uint32_t fetchdat)
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{
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uint8_t temp, temp2 = AL;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab(); if (cpu_state.abrt) return 1;
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if (AL == temp) seteab(getr8(cpu_reg));
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else AL = temp;
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if (cpu_state.abrt) return 1;
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setsub8(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG_b_a32(uint32_t fetchdat)
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{
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uint8_t temp, temp2 = AL;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab(); if (cpu_state.abrt) return 1;
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if (AL == temp) seteab(getr8(cpu_reg));
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else AL = temp;
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if (cpu_state.abrt) return 1;
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setsub8(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG_w_a16(uint32_t fetchdat)
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{
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uint16_t temp, temp2 = AX;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
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else AX = temp;
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if (cpu_state.abrt) return 1;
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setsub16(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG_w_a32(uint32_t fetchdat)
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{
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uint16_t temp, temp2 = AX;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
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else AX = temp;
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if (cpu_state.abrt) return 1;
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setsub16(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG_l_a16(uint32_t fetchdat)
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{
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uint32_t temp, temp2 = EAX;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal(); if (cpu_state.abrt) return 1;
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if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
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else EAX = temp;
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if (cpu_state.abrt) return 1;
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setsub32(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG_l_a32(uint32_t fetchdat)
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{
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uint32_t temp, temp2 = EAX;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal(); if (cpu_state.abrt) return 1;
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if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
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else EAX = temp;
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if (cpu_state.abrt) return 1;
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setsub32(temp2, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
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return 0;
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}
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static int opCMPXCHG8B_a16(uint32_t fetchdat)
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{
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uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal();
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temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
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if (EAX == temp && EDX == temp_hi)
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{
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seteal(EBX);
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writememl(easeg, cpu_state.eaaddr+4, ECX);
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}
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else
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{
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EAX = temp;
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EDX = temp_hi;
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}
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if (cpu_state.abrt) return 0;
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flags_rebuild();
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if (temp == temp2 && temp_hi == temp2_hi)
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cpu_state.flags |= Z_FLAG;
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else
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cpu_state.flags &= ~Z_FLAG;
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cycles -= (cpu_mod == 3) ? 6 : 10;
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return 0;
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}
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static int opCMPXCHG8B_a32(uint32_t fetchdat)
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{
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uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal();
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temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
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if (EAX == temp && EDX == temp_hi)
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{
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seteal(EBX);
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writememl(easeg, cpu_state.eaaddr+4, ECX);
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}
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else
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{
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EAX = temp;
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EDX = temp_hi;
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}
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if (cpu_state.abrt) return 0;
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flags_rebuild();
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if (temp == temp2 && temp_hi == temp2_hi)
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cpu_state.flags |= Z_FLAG;
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else
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cpu_state.flags &= ~Z_FLAG;
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cycles -= (cpu_mod == 3) ? 6 : 10;
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return 0;
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}
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static int opXADD_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab(); if (cpu_state.abrt) return 1;
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seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
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setadd8(temp, getr8(cpu_reg));
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setr8(cpu_reg, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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static int opXADD_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteab(); if (cpu_state.abrt) return 1;
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seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
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setadd8(temp, getr8(cpu_reg));
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setr8(cpu_reg, temp);
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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static int opXADD_w_a16(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
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setadd16(temp, cpu_state.regs[cpu_reg].w);
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cpu_state.regs[cpu_reg].w = temp;
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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static int opXADD_w_a32(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
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setadd16(temp, cpu_state.regs[cpu_reg].w);
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cpu_state.regs[cpu_reg].w = temp;
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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static int opXADD_l_a16(uint32_t fetchdat)
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{
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uint32_t temp;
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal(); if (cpu_state.abrt) return 1;
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seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
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setadd32(temp, cpu_state.regs[cpu_reg].l);
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cpu_state.regs[cpu_reg].l = temp;
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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static int opXADD_l_a32(uint32_t fetchdat)
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{
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uint32_t temp;
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = geteal(); if (cpu_state.abrt) return 1;
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seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
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setadd32(temp, cpu_state.regs[cpu_reg].l);
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cpu_state.regs[cpu_reg].l = temp;
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
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return 0;
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}
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