182c737921
The SMC FDC37C665 Super I/O chip's IDE handler is now disabled for the Rise Computer R418 (the real board by passes that chip's IDE and uses the SiS 496B IDE controller so this is correct and not a hack), fixes hard disks disappearing on soft reset.
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include <stdlib.h>
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#include "ibm.h"
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#include "device.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "sis496.h"
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typedef struct sis496_t
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{
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uint8_t pci_conf[256];
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} sis496_t;
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sis496_t sis496;
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void sis496_recalcmapping(void)
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{
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int c;
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for (c = 0; c < 8; c++)
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{
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uint32_t base = 0xc0000 + (c << 15);
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if (sis496.pci_conf[0x44] & (1 << c))
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{
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switch (sis496.pci_conf[0x45] & 3)
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{
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case 0:
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 1:
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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}
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}
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else
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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flushmmucache();
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shadowbios = (sis496.pci_conf[0x44] & 0xf0);
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}
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void sis496_write(int func, int addr, uint8_t val, void *p)
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{
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switch (addr)
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{
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case 0x44: /*Shadow configure*/
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if ((sis496.pci_conf[0x44] & val) ^ 0xf0)
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{
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sis496.pci_conf[0x44] = val;
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sis496_recalcmapping();
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}
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break;
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case 0x45: /*Shadow configure*/
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if ((sis496.pci_conf[0x45] & val) ^ 0x01)
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{
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sis496.pci_conf[0x45] = val;
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sis496_recalcmapping();
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}
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break;
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}
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if ((addr >= 4 && addr < 8) || addr >= 0x40)
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sis496.pci_conf[addr] = val;
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}
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uint8_t sis496_read(int func, int addr, void *p)
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{
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return sis496.pci_conf[addr];
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}
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void sis496_reset(void)
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{
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memset(&sis496, 0, sizeof(sis496_t));
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sis496.pci_conf[0x00] = 0x39; /*SiS*/
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sis496.pci_conf[0x01] = 0x10;
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sis496.pci_conf[0x02] = 0x96; /*496/497*/
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sis496.pci_conf[0x03] = 0x04;
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sis496.pci_conf[0x04] = 7;
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sis496.pci_conf[0x05] = 0;
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sis496.pci_conf[0x06] = 0x80;
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sis496.pci_conf[0x07] = 0x02;
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sis496.pci_conf[0x08] = 2; /*Device revision*/
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sis496.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis496.pci_conf[0x0a] = 0x00;
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sis496.pci_conf[0x0b] = 0x06;
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sis496.pci_conf[0x0e] = 0x00; /*Single function device*/
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}
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void sis496_pci_reset(void)
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{
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uint8_t val = 0;
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val = sis496_read(0, 0x44, NULL); /* Read current value of 0x44. */
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sis496_write(0, 0x44, val & 0xf, NULL); /* Turn off shadow BIOS but keep the lower 4 bits. */
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}
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void sis496_init(void)
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{
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pci_add_specific(5, sis496_read, sis496_write, NULL);
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sis496_reset();
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pci_reset_handler.pci_master_reset = sis496_pci_reset;
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}
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void sis496_close(void *p)
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{
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sis496_t *sis496 = (sis496_t *)p;
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free(sis496);
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}
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