219 lines
7.5 KiB
C
219 lines
7.5 KiB
C
// ID
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#define CIRRUS_ID_CLGD6225 (0x02<<2)
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#define CIRRUS_ID_CLGD5402 (0x06<<2) /* Also Acumos AVGA2 */
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#define CIRRUS_ID_CLGD7542 (0x0B<<2) /* Nordic */
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#define CIRRUS_ID_CLGD7543 (0x0C<<2) /* Viking - guess */
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#define CIRRUS_ID_CLGD7541 (0x0D<<2) /* Nordic Lite */
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#define CIRRUS_ID_CLGD6215 (0x12<<2)
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#define CIRRUS_ID_CLGD6235 (0x22<<2) /* Also 5402 */
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#define CIRRUS_ID_CLGD5422 (0x23<<2)
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#define CIRRUS_ID_CLGD5426 (0x24<<2)
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#define CIRRUS_ID_CLGD5424 (0x25<<2) /* Also 5422-80 */
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#define CIRRUS_ID_CLGD5428 (0x26<<2)
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#define CIRRUS_ID_CLGD5429 (0x27<<2)
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#define CIRRUS_ID_CLGD5430 (0x28<<2)
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#define CIRRUS_ID_CLGD5432 0xA2
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#define CIRRUS_ID_CLGD5434O (0x29<<2) /* O = obsolete, never used? */
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#define CIRRUS_ID_CLGD5434 (0x2A<<2)
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#define CIRRUS_ID_CLGD5436 (0x2B<<2)
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#define CIRRUS_ID_CLGD5436U (0x3A<<2)
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#define CIRRUS_ID_CLGD5440 (0x2C<<2)
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#define CIRRUS_ID_CLGD5442 (0x2D<<2)
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#define CIRRUS_ID_CLGD5446 (0x2E<<2)
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#define CIRRUS_ID_CLGD5455 (0x2F<<2) /* Laguna 3D */
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#define CIRRUS_ID_CLGD6205 (0x32<<2) /* Laguna 3D */
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#define CIRRUS_ID_CLGD5462 (0x34<<2) /* Laguna */
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#define CIRRUS_ID_CLGD5464 (0xD5) /* Laguna BD */
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#define CIRRUS_ID_CLGD5465 (0xD6) /* Laguna 3D */
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA 0x00
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#define CIRRUS_SR7_BPP_SVGA 0x01
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#define CIRRUS_SR7_BPP_MASK 0x0e
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#define CIRRUS_SR7_BPP_8 0x00
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
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#define CIRRUS_SR7_BPP_24 0x04
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#define CIRRUS_SR7_BPP_16 0x06
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#define CIRRUS_SR7_BPP_32 0x08
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#define CIRRUS_SR7_ISAADDR_MASK 0xe0
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k 0x08
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#define CIRRUS_MEMSIZE_1M 0x10
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#define CIRRUS_MEMSIZE_2M 0x18
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW 0x01
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#define CIRRUS_CURSOR_HIDDENPEL 0x02
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#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST 0x10
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#define CIRRUS_BUSTYPE_PCI 0x20
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#define CIRRUS_BUSTYPE_VLBSLOW 0x30
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#define CIRRUS_BUSTYPE_ISA 0x38
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#define CIRRUS_MMIO_ENABLE 0x04
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#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
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// control 0x0b
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#define CIRRUS_BANKING_DUAL 0x01
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#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS 0x01
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#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
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#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
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#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
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#define CIRRUS_BLTMODE_COLOREXPAND 0x80
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
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#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
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#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
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#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
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#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
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// control 0x31
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#define CIRRUS_BLT_BUSY 0x01
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#define CIRRUS_BLT_START 0x02
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#define CIRRUS_BLT_RESET 0x04
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#define CIRRUS_BLT_FIFOUSED 0x10
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#define CIRRUS_BLT_AUTOSTART 0x80
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// control 0x32
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#define CIRRUS_ROP_0 0x00
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#define CIRRUS_ROP_SRC_AND_DST 0x05
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#define CIRRUS_ROP_NOP 0x06
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#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
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#define CIRRUS_ROP_NOTDST 0x0b
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#define CIRRUS_ROP_SRC 0x0d
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#define CIRRUS_ROP_1 0x0e
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#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
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#define CIRRUS_ROP_SRC_XOR_DST 0x59
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#define CIRRUS_ROP_SRC_OR_DST 0x6d
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
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#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
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#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
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#define CIRRUS_ROP_NOTSRC 0xd0
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#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
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#define CIRRUS_ROP_NOP_INDEX 2
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#define CIRRUS_ROP_SRC_INDEX 5
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
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#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
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#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
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#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
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#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
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#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
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#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
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#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
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#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
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#define CIRRUS_MMIO_BLTMODE 0x18 // byte
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#define CIRRUS_MMIO_BLTROP 0x1a // byte
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#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
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#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
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#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
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#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
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#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
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#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
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#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
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#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
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#define CIRRUS_PNPMMIO_SIZE 0x1000
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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typedef struct clgd_t
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{
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mem_mapping_t mmio_mapping;
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svga_t svga;
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cl_ramdac_t ramdac;
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rom_t bios_rom;
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PALETTE hiddenpal;
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uint32_t vram_size;
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uint8_t vram_code;
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uint32_t linear_mmio_mask;
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uint32_t bank[2];
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uint32_t limit[2];
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uint32_t ramptr;
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int src_counter;
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uint8_t *src_ptr;
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uint8_t *src_ptr_end;
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struct
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{
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uint8_t bpp;
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uint32_t bg_col, fg_col;
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uint16_t width, height;
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uint16_t dst_pitch, src_pitch;
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int32_t dst_addr, src_addr;
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uint8_t mask, mode, rop, modeext;
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uint32_t blttc, blttcmask;
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uint16_t ld_start_x, ld_start_y, ld_end_x, ld_end_y;
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uint8_t ld_ls_inc, ld_ls_ro, ld_ls_mask, ld_ls_ac;
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uint16_t bres_k1, bres_k3, bres_err, bres_dm;
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uint8_t bres_dir, ld_mode, blt_status;
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uint32_t dst_addr_backup, src_addr_backup;
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uint16_t width_backup, height_internal;
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int x_count;
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uint8_t buf[CIRRUS_BLTBUFSIZE];
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uint16_t pixel_width, pixel_height;
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} blt;
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} clgd_t;
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typedef void (*cirrus_bitblt_rop_t) (clgd_t *clgd, svga_t *svga,
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uint8_t * dst, const uint8_t * src,
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int dstpitch, int srcpitch,
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int bltwidth, int bltheight);
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typedef void (*cirrus_fill_t)(clgd_t *clgd, svga_t *svga,
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uint8_t *dst, int dst_pitch, int width, int height);
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cirrus_bitblt_rop_t cirrus_rop;
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extern device_t gd5422_device;
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extern device_t gd5429_device;
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extern device_t gd5430_device;
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extern device_t dia5430_device;
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extern device_t gd5434_device;
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extern device_t gd5436_device;
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extern device_t gd5440_device;
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extern device_t gd5446_device;
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extern device_t gd6235_device;
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clgd_t *clgd;
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void clgd_recalctimings(svga_t *svga);
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void cirrus_update_memory_access(clgd_t *clgd);
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void cirrus_write(uint32_t addr, uint8_t val, void *p);
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uint8_t cirrus_read(uint32_t addr, void *p); |