dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
217 lines
6.2 KiB
C
217 lines
6.2 KiB
C
static int opXCHG_b_a16(uint32_t fetchdat)
|
|
{
|
|
uint8_t temp;
|
|
fetch_ea_16(fetchdat);
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
|
setr8(cpu_reg, temp);
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_b_a32(uint32_t fetchdat)
|
|
{
|
|
uint8_t temp;
|
|
fetch_ea_32(fetchdat);
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
|
setr8(cpu_reg, temp);
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opXCHG_w_a16(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp;
|
|
fetch_ea_16(fetchdat);
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
|
cpu_state.regs[cpu_reg].w = temp;
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_w_a32(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp;
|
|
fetch_ea_32(fetchdat);
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
|
cpu_state.regs[cpu_reg].w = temp;
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opXCHG_l_a16(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp;
|
|
fetch_ea_16(fetchdat);
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
|
cpu_state.regs[cpu_reg].l = temp;
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_l_a32(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp;
|
|
fetch_ea_32(fetchdat);
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
|
cpu_state.regs[cpu_reg].l = temp;
|
|
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
|
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int opXCHG_AX_BX(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = BX;
|
|
BX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_CX(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = CX;
|
|
CX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_DX(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = DX;
|
|
DX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_SI(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = SI;
|
|
SI = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_DI(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = DI;
|
|
DI = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_BP(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = BP;
|
|
BP = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_AX_SP(uint32_t fetchdat)
|
|
{
|
|
uint16_t temp = AX;
|
|
AX = SP;
|
|
SP = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
|
|
static int opXCHG_EAX_EBX(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = EBX;
|
|
EBX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_ECX(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = ECX;
|
|
ECX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_EDX(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = EDX;
|
|
EDX = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_ESI(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = ESI;
|
|
ESI = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_EDI(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = EDI;
|
|
EDI = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_EBP(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = EBP;
|
|
EBP = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
static int opXCHG_EAX_ESP(uint32_t fetchdat)
|
|
{
|
|
uint32_t temp = EAX;
|
|
EAX = ESP;
|
|
ESP = temp;
|
|
CLOCK_CYCLES(3);
|
|
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
|
|
return 0;
|
|
}
|
|
|
|
|
|
#define opBSWAP(reg) \
|
|
static int opBSWAP_ ## reg(uint32_t fetchdat) \
|
|
{ \
|
|
reg = (reg >> 24) | ((reg >> 8) & 0xff00) | ((reg << 8) & 0xff0000) | ((reg << 24) & 0xff000000); \
|
|
CLOCK_CYCLES(1); \
|
|
PREFETCH_RUN(1, 1, -1, 0,0,0,0, 0); \
|
|
return 0; \
|
|
}
|
|
|
|
opBSWAP(EAX)
|
|
opBSWAP(EBX)
|
|
opBSWAP(ECX)
|
|
opBSWAP(EDX)
|
|
opBSWAP(ESI)
|
|
opBSWAP(EDI)
|
|
opBSWAP(EBP)
|
|
opBSWAP(ESP)
|