410 lines
12 KiB
C
410 lines
12 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C391/392 chipset.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/plat_unused.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_OPTI391_LOG
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int opti391_do_log = ENABLE_OPTI391_LOG;
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static void
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opti391_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti391_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define opti391_log(fmt, ...)
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#endif
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typedef struct mem_remapping_t {
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uint32_t phys;
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uint32_t virt;
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} mem_remapping_t;
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typedef struct opti391_t {
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uint8_t type;
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uint8_t reg_base;
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uint8_t min_reg;
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uint8_t max_reg;
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uint16_t shadowed;
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uint16_t old_start;
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uint8_t index;
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uint8_t regs[256];
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} opti391_t;
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static void
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opti391_recalcremap(opti391_t *dev)
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{
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if (dev->type < 2) {
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if ((mem_size > 8192) || (dev->shadowed & 0x0ff0) ||
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!(dev->regs[0x01] & 0x0f) || !(dev->regs[0x01] & 0x10)) {
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mem_remap_top_ex(0, dev->old_start);
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dev->old_start = 1024;
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} else {
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mem_remap_top_ex(0, dev->old_start);
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dev->old_start = (dev->regs[0x01] & 0x0f) * 1024;
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mem_remap_top_ex(-256, dev->old_start);
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}
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}
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}
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static void
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opti391_shadow_recalc(opti391_t *dev)
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{
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uint32_t base;
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uint8_t sh_enable;
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uint8_t sh_master;
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uint8_t sh_wp;
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uint8_t sh_write_internal;
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shadowbios = shadowbios_write = 0;
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/* F0000-FFFFF */
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sh_enable = (dev->regs[0x02] & 0x80);
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if (sh_enable)
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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dev->shadowed |= 0xf000;
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sh_write_internal = (dev->regs[0x06] & 0x40);
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/* D0000-EFFFF */
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for (uint8_t i = 0; i < 8; i++) {
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base = 0xd0000 + (i << 14);
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if (base >= 0xe0000) {
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sh_master = (dev->regs[0x02] & 0x20);
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sh_wp = (dev->regs[0x02] & 0x08);
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} else {
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sh_master = (dev->regs[0x02] & 0x40);
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sh_wp = (dev->regs[0x02] & 0x10);
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}
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sh_enable = dev->regs[0x03] & (1 << i);
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if (sh_master) {
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if (sh_enable) {
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if (sh_wp)
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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else
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << (i + 4));
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} else if (sh_write_internal) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << (i + 4));
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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dev->shadowed &= ~(1 << (i + 4));
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}
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} else if (sh_write_internal) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << (i + 4));
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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dev->shadowed &= ~(1 << (i + 4));
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}
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}
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/* C0000-CFFFF */
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sh_master = (dev->regs[0x06] & 0x10); /* OPTi 391 datasheet erratum! */
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sh_wp = (dev->regs[0x06] & 0x20);
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for (uint8_t i = 0; i < 4; i++) {
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base = 0xc0000 + (i << 14);
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sh_enable = dev->regs[0x06] & (1 << i);
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if (sh_master) {
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if (sh_enable) {
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if (sh_wp)
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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else
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << i);
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} else if (sh_write_internal) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << i);
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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dev->shadowed &= ~(1 << i);
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}
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} else if (sh_write_internal) {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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dev->shadowed |= (1 << i);
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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dev->shadowed &= ~(1 << i);
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}
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}
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opti391_recalcremap(dev);
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}
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static void
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opti391_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti391_t *dev = (opti391_t *) priv;
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opti391_log("[W] %04X = %02X\n", addr, val);
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switch (addr) {
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default:
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break;
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case 0x22:
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dev->index = val;
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break;
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case 0x24:
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opti391_log("OPTi 391: dev->regs[%02x] = %02x\n", dev->index, val);
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if ((dev->index <= 0x01) && (dev->type < 2)) switch (dev->index) {
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case 0x00:
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if (!(dev->regs[0x10] & 0x20) && (val & 0x20)) {
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softresetx86(); /* Pulse reset! */
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cpu_set_edx();
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flushmmucache();
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}
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dev->regs[dev->index + 0x10] = val;
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break;
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case 0x01:
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dev->regs[dev->index + 0x10] = val;
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reset_on_hlt = !!(val & 0x02);
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break;
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} else switch (dev->index - dev->reg_base) {
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default:
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break;
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case 0x00:
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if (dev->type == 2) {
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reset_on_hlt = !!(val & 0x02);
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if (!(dev->regs[dev->index - dev->reg_base] & 0x01) && (val & 0x01)) {
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softresetx86(); /* Pulse reset! */
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cpu_set_edx();
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flushmmucache();
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}
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dev->regs[dev->index - dev->reg_base] =
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(dev->regs[dev->index - dev->reg_base] & 0xc0) | (val & 0x3f);
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}
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break;
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case 0x01:
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dev->regs[dev->index - dev->reg_base] = val;
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if (dev->type == 2) {
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cpu_cache_ext_enabled = !!(dev->regs[0x01] & 0x10);
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cpu_update_waitstates();
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} else
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opti391_recalcremap(dev);
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break;
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case 0x05:
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if (dev->type == 2)
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dev->regs[dev->index - dev->reg_base] = val & 0xf8;
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else
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dev->regs[dev->index - dev->reg_base] = val;
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break;
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case 0x04:
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case 0x09:
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case 0x0a:
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case 0x0b:
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dev->regs[dev->index - dev->reg_base] = val;
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break;
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case 0x07:
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dev->regs[dev->index - dev->reg_base] = val;
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if (dev->type < 2) {
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mem_a20_alt = val & 0x08;
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mem_a20_recalc();
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}
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break;
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case 0x08:
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if (dev->type == 2)
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dev->regs[dev->index - dev->reg_base] = val & 0xe3;
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else {
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dev->regs[dev->index - dev->reg_base] = val;
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x40);
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cpu_update_waitstates();
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}
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break;
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case 0x0c:
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case 0x0d:
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if (dev->type < 2)
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dev->regs[dev->index - dev->reg_base] = val;
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break;
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case 0x02:
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case 0x03:
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case 0x06:
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opti391_log("Write %02X: %02X\n", dev->index - dev->reg_base, val);
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dev->regs[dev->index - dev->reg_base] = val;
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opti391_shadow_recalc(dev);
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break;
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}
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dev->index = 0xff;
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break;
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}
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}
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static uint8_t
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opti391_read(uint16_t addr, void *priv)
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{
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opti391_t *dev = (opti391_t *) priv;
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uint8_t ret = 0xff;
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if (addr == 0x24) {
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if ((dev->index <= 0x01) && (dev->type < 2))
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ret = dev->regs[dev->index + 0x10];
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else if ((dev->index >= dev->min_reg) && (dev->index <= dev->max_reg))
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ret = dev->regs[dev->index - dev->reg_base];
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dev->index = 0xff;
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}
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opti391_log("[R] %04X = %02X\n", addr, ret);
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return ret;
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}
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static void
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opti391_close(void *priv)
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{
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opti391_t *dev = (opti391_t *) priv;
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free(dev);
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}
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static void *
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opti391_init(const device_t *info)
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{
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opti391_t *dev = (opti391_t *) calloc(1, sizeof(opti391_t));
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io_sethandler(0x0022, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
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dev->type = info->local;
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if (info->local == 2) {
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dev->reg_base = 0x20;
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dev->min_reg = 0x20;
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dev->max_reg = 0x2b;
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dev->regs[0x02] = 0x84;
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dev->regs[0x04] = 0x07;
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dev->regs[0x05] = 0xf0;
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dev->regs[0x06] = 0x30;
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dev->regs[0x07] = 0x91;
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dev->regs[0x08] = 0x80;
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dev->regs[0x09] = 0x10;
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dev->regs[0x0a] = 0x80;
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dev->regs[0x0b] = 0x10;
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} else {
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dev->reg_base = 0x0f;
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dev->min_reg = 0x10;
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dev->max_reg = 0x1c;
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dev->regs[0x01] = 0x01;
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dev->regs[0x02] = 0xe0;
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if (info->local == 1)
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/* Guess due to no OPTi 48x datasheet. */
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dev->regs[0x04] = 0x07;
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else
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dev->regs[0x04] = 0x77;
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dev->regs[0x05] = 0x60;
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dev->regs[0x06] = 0x10;
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dev->regs[0x07] = 0x50;
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if (info->local == 1) {
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/* Guess due to no OPTi 48x datasheet. */
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dev->regs[0x09] = 0x80; /* Non-Cacheable Block 1 */
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dev->regs[0x0b] = 0x80; /* Non-Cacheable Block 2 */
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dev->regs[0x0d] = 0x91; /* Cacheable Area */
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} else {
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dev->regs[0x09] = 0xe0; /* Non-Cacheable Block 1 */
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dev->regs[0x0b] = 0x10; /* Non-Cacheable Block 2 */
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dev->regs[0x0d] = 0x80; /* Cacheable Area */
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}
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dev->regs[0x0a] = 0x10;
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dev->regs[0x0c] = 0x10;
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}
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dev->old_start = 1024;
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opti391_shadow_recalc(dev);
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return dev;
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}
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const device_t opti381_device = {
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.name = "OPTi 82C381",
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.internal_name = "opti381",
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.flags = 0,
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.local = 0,
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.init = opti391_init,
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.close = opti391_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t opti481_device = {
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.name = "OPTi 82C481",
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.internal_name = "opti481",
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.flags = 0,
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.local = 1,
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.init = opti391_init,
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.close = opti391_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t opti391_device = {
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.name = "OPTi 82C391",
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.internal_name = "opti391",
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.flags = 0,
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.local = 2,
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.init = opti391_init,
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.close = opti391_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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