742 lines
16 KiB
C
742 lines
16 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the STPC series of SoCs.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/port_92.h>
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#include <86box/usb.h>
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#include <86box/chipset.h>
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#define STPC_NB_CLIENT 0x01
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#define STPC_ISAB_CLIENT 0x02
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#define STPC_ISAB_CONSUMER2 0x04
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#define STPC_IDE_ATLAS 0x08
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#define STPC_USB 0x10
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typedef struct stpc_t
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{
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uint32_t local;
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/* Main registers (port 22h/23h) */
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uint8_t reg_offset;
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uint8_t regs[256];
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/* Host bus interface */
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uint16_t host_base;
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uint8_t host_offset;
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uint8_t host_regs[256];
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/* Local bus */
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uint16_t localbus_base;
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uint8_t localbus_offset;
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uint8_t localbus_regs[256];
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/* PCI devices */
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uint8_t pci_conf[4][256];
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usb_t *usb;
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} stpc_t;
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#define ENABLE_STPC_LOG 1
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#ifdef ENABLE_STPC_LOG
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int stpc_do_log = ENABLE_STPC_LOG;
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static void
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stpc_log(const char *fmt, ...)
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{
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va_list ap;
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if (stpc_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define stpc_log(fmt, ...)
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#endif
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static void
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stpc_recalcmapping(stpc_t *dev)
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{
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uint8_t reg, bitpair;
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uint32_t base, size;
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int state;
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shadowbios = 0;
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shadowbios_write = 0;
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for (reg = 0; reg <= 3; reg++) {
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for (bitpair = 0; bitpair <= (reg == 3 ? 0 : 3); bitpair++) {
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if (reg == 3) {
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size = 0x10000;
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base = 0xf0000;
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} else {
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size = 0x4000;
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base = 0xc0000 + (size * ((reg * 4) + bitpair));
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}
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stpc_log("STPC: Shadowing for %05x-%05x (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
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state = 0;
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if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
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stpc_log(" w on");
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state |= MEM_WRITE_INTERNAL;
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if (base >= 0xe0000)
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shadowbios_write |= 1;
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} else {
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stpc_log(" w off");
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state |= MEM_WRITE_EXTANY;
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}
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if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
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stpc_log("; r on\n");
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state |= MEM_READ_INTERNAL;
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if (base >= 0xe0000)
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shadowbios |= 1;
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} else {
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stpc_log("; r off\n");
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state |= MEM_READ_EXTANY;
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}
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mem_set_mem_state(base, size, state);
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}
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}
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flushmmucache();
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}
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static void
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stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
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{
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mem_set_mem_state_smram(smm, addr, size, is_smram);
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}
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static void
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stpc_host_write(uint16_t addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: host_write(%04X, %02X)\n", addr, val);
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if (addr == dev->host_base)
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dev->host_offset = val;
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else if (addr == dev->host_base + 4)
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dev->host_regs[dev->host_offset] = val;
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}
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static uint8_t
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stpc_host_read(uint16_t addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (addr == dev->host_base)
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ret = dev->host_offset;
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else if (addr == dev->host_base + 4)
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ret = dev->host_regs[dev->host_offset];
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else
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ret = 0xff;
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stpc_log("STPC: host_read(%04X) = %02X\n", addr, ret);
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return ret;
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}
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static void
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stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: localbus_write(%04X, %02X)\n", addr, val);
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if (addr == dev->localbus_base)
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dev->localbus_offset = val;
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else if (addr == dev->localbus_base + 4)
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dev->localbus_regs[addr] = val;
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}
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static uint8_t
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stpc_localbus_read(uint16_t addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (addr == dev->localbus_base)
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ret = dev->localbus_offset;
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else if (addr == dev->localbus_base + 4)
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ret = dev->localbus_regs[dev->localbus_offset];
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else
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ret = 0xff;
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stpc_log("STPC: localbus_read(%04X) = %02X\n", addr, ret);
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return ret;
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}
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static void
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stpc_nb_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: nb_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x04: case 0x06: case 0x07: case 0x08:
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case 0x09: case 0x0a: case 0x0b: case 0x0e:
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case 0x51: case 0x53: case 0x54:
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return;
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case 0x05:
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val &= 0x01;
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break;
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case 0x50:
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val &= 0x1f;
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break;
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case 0x52:
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val &= 0x70;
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break;
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}
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dev->pci_conf[0][addr] = val;
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}
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static uint8_t
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stpc_nb_read(int func, int addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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else
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ret = dev->pci_conf[0][addr];
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stpc_log("STPC: nb_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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static void
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stpc_ide_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: ide_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x04: case 0x06: case 0x07: case 0x08:
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case 0x09: case 0x0a: case 0x0b: case 0x0e:
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return;
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case 0x05:
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val &= 0x01;
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break;
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}
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dev->pci_conf[2][addr] = val;
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}
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static uint8_t
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stpc_ide_read(int func, int addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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else
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ret = dev->pci_conf[2][addr];
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stpc_log("STPC: ide_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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static void
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stpc_isab_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) {
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stpc_ide_write(0, addr, val, priv);
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return;
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}
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stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x04: case 0x06: case 0x07: case 0x08:
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case 0x09: case 0x0a: case 0x0b: case 0x0e:
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return;
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case 0x05:
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val &= 0x01;
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break;
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}
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dev->pci_conf[1][addr] = val;
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}
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static uint8_t
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stpc_isab_read(int func, int addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func == 1 && !(dev->local & STPC_IDE_ATLAS))
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return stpc_ide_read(0, addr, priv);
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else if (func > 0)
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ret = 0xff;
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else
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ret = dev->pci_conf[1][addr];
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stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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static void
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stpc_usb_write(int func, int addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: usb_write(%d, %02X, %02X)\n", func, addr, val);
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if (func > 0)
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return;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x04: case 0x06: case 0x07: case 0x08:
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case 0x09: case 0x0a: case 0x0b: case 0x0e:
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case 0x10:
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return;
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case 0x05:
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val &= 0x01;
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break;
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case 0x11:
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dev->pci_conf[3][addr] = val & 0xf0;
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ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
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break;
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case 0x12: case 0x13:
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dev->pci_conf[3][addr] = val;
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ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
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break;
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}
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dev->pci_conf[3][addr] = val;
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}
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static uint8_t
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stpc_usb_read(int func, int addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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else
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ret = dev->pci_conf[3][addr];
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stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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}
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static void
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stpc_remap_host(stpc_t *dev, uint16_t host_base)
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{
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stpc_log("STPC: Remapping host bus from %04X to %04X\n", dev->host_base, host_base);
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io_removehandler(dev->host_base, 5,
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stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
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if (host_base) {
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io_sethandler(host_base, 5,
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stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
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}
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dev->host_base = host_base;
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}
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static void
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stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
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{
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stpc_log("STPC: Remapping local bus from %04X to %04X\n", dev->localbus_base, localbus_base);
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io_removehandler(dev->localbus_base, 5,
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stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
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if (localbus_base) {
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io_sethandler(localbus_base, 5,
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stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
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}
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dev->localbus_base = localbus_base;
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}
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static void
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stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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stpc_log("STPC: reg_write(%04X, %02X)\n", addr, val);
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if (addr == 0x22) {
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dev->reg_offset = val;
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} else {
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stpc_log("STPC: regs[%02X] = %02X\n", dev->reg_offset, val);
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switch (dev->reg_offset) {
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case 0x12:
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if (dev->regs[0x10] == 0x07)
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stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
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else if (dev->regs[0x10] == 0x06)
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stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
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break;
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case 0x13:
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if (dev->regs[0x10] == 0x07)
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stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
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else if (dev->regs[0x10] == 0x06)
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stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
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break;
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case 0x21:
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val &= 0xfe;
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break;
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case 0x22:
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val &= 0x7f;
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break;
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case 0x25: case 0x26: case 0x27: case 0x28:
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if (dev->reg_offset == 0x28) {
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val &= 0xe3;
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stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
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}
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dev->regs[dev->reg_offset] = val;
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stpc_recalcmapping(dev);
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break;
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case 0x29:
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val &= 0x0f;
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break;
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case 0x36:
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val &= 0x3f;
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break;
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case 0x52: case 0x53: case 0x54: case 0x55:
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stpc_log("STPC: Set IRQ routing: INT %c -> %d\n", 0x41 + ((dev->reg_offset & 0x03) ^ 0x02), (val & 0x80) ? (val & 0xf) : -1);
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val &= 0x8f;
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pci_set_irq_routing(PCI_INTA + ((dev->reg_offset & 0x03) ^ 0x02), (val & 0x80) ? (val & 0xf) : PCI_IRQ_DISABLED);
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break;
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case 0x56: case 0x57:
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/* ELCR goes here */
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break;
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}
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dev->regs[dev->reg_offset] = val;
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}
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}
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static uint8_t
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stpc_reg_read(uint16_t addr, void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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uint8_t ret;
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if (addr == 0x22)
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ret = dev->reg_offset;
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else if (dev->reg_offset >= 0xc0)
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return 0xff; /* Cyrix CPU registers: let the CPU code handle those */
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else
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ret = dev->regs[dev->reg_offset];
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stpc_log("STPC: reg_read(%04X) = %02X\n", addr, ret);
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return ret;
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}
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|
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|
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static void
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stpc_reset(void *priv)
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{
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stpc_t *dev = (stpc_t *) priv;
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|
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stpc_log("STPC: reset()\n");
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|
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memset(dev->regs, 0, sizeof(dev->regs));
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dev->regs[0x7b] = 0xff;
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|
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io_removehandler(0x22, 2,
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stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
|
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io_sethandler(0x22, 2,
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stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
|
|
}
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static void
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stpc_setup(stpc_t *dev)
|
|
{
|
|
stpc_log("STPC: setup()\n");
|
|
|
|
/* Northbridge */
|
|
dev->pci_conf[0][0x00] = 0x4a;
|
|
dev->pci_conf[0][0x01] = 0x10;
|
|
if (dev->local & STPC_NB_CLIENT) {
|
|
dev->pci_conf[0][0x02] = 0x64;
|
|
dev->pci_conf[0][0x03] = 0x05;
|
|
} else {
|
|
dev->pci_conf[0][0x02] = 0x0a;
|
|
dev->pci_conf[0][0x03] = 0x02;
|
|
}
|
|
|
|
dev->pci_conf[0][0x04] = 0x07;
|
|
|
|
dev->pci_conf[0][0x06] = 0x80;
|
|
dev->pci_conf[0][0x07] = 0x02;
|
|
|
|
dev->pci_conf[0][0x0b] = 0x06;
|
|
|
|
/* ISA Bridge */
|
|
dev->pci_conf[1][0x00] = 0x4a;
|
|
dev->pci_conf[1][0x01] = 0x10;
|
|
if (dev->local & STPC_ISAB_CLIENT) {
|
|
dev->pci_conf[1][0x02] = 0xcc;
|
|
dev->pci_conf[1][0x03] = 0x55;
|
|
} else if (dev->local & STPC_ISAB_CONSUMER2) {
|
|
dev->pci_conf[1][0x02] = 0x0b;
|
|
dev->pci_conf[1][0x03] = 0x02;
|
|
} else {
|
|
dev->pci_conf[1][0x02] = 0x10;
|
|
dev->pci_conf[1][0x03] = 0x02;
|
|
}
|
|
|
|
dev->pci_conf[1][0x04] = 0x0f;
|
|
|
|
dev->pci_conf[1][0x06] = 0x80;
|
|
dev->pci_conf[1][0x07] = 0x02;
|
|
|
|
dev->pci_conf[1][0x0a] = 0x01;
|
|
dev->pci_conf[1][0x0b] = 0x06;
|
|
|
|
dev->pci_conf[1][0x0e] = 0x40;
|
|
|
|
/* IDE */
|
|
dev->pci_conf[2][0x00] = 0x4a;
|
|
dev->pci_conf[2][0x01] = 0x10;
|
|
if (dev->local & STPC_IDE_ATLAS) {
|
|
dev->pci_conf[2][0x02] = 0x28;
|
|
dev->pci_conf[2][0x03] = 0x02;
|
|
} else {
|
|
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
|
|
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
|
|
}
|
|
|
|
dev->pci_conf[2][0x06] = 0x80;
|
|
dev->pci_conf[2][0x07] = 0x02;
|
|
|
|
dev->pci_conf[2][0x09] = 0x8a;
|
|
dev->pci_conf[2][0x0a] = 0x01;
|
|
dev->pci_conf[2][0x0b] = 0x01;
|
|
|
|
dev->pci_conf[2][0x0e] = 0x40;
|
|
|
|
dev->pci_conf[2][0x10] = 0x01;
|
|
dev->pci_conf[2][0x14] = 0x01;
|
|
dev->pci_conf[2][0x18] = 0x01;
|
|
dev->pci_conf[2][0x1c] = 0x01;
|
|
|
|
dev->pci_conf[2][0x40] = 0x60;
|
|
dev->pci_conf[2][0x41] = 0x97;
|
|
dev->pci_conf[2][0x42] = 0x60;
|
|
dev->pci_conf[2][0x43] = 0x97;
|
|
dev->pci_conf[2][0x44] = 0x60;
|
|
dev->pci_conf[2][0x45] = 0x97;
|
|
dev->pci_conf[2][0x46] = 0x60;
|
|
dev->pci_conf[2][0x47] = 0x97;
|
|
|
|
/* USB */
|
|
if (dev->usb) {
|
|
dev->pci_conf[3][0x00] = 0x4a;
|
|
dev->pci_conf[3][0x01] = 0x10;
|
|
dev->pci_conf[3][0x02] = 0x30;
|
|
dev->pci_conf[3][0x03] = 0x02;
|
|
|
|
dev->pci_conf[3][0x06] = 0x80;
|
|
dev->pci_conf[3][0x07] = 0x02;
|
|
|
|
dev->pci_conf[3][0x09] = 0x10;
|
|
dev->pci_conf[3][0x0a] = 0x03;
|
|
dev->pci_conf[3][0x0b] = 0x0c;
|
|
|
|
dev->pci_conf[3][0x0e] = 0x40;
|
|
}
|
|
|
|
/* PCI setup */
|
|
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
|
|
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
|
|
}
|
|
|
|
|
|
static void
|
|
stpc_close(void *priv)
|
|
{
|
|
stpc_t *dev = (stpc_t *) priv;
|
|
|
|
stpc_log("STPC: close()\n");
|
|
|
|
free(dev);
|
|
}
|
|
|
|
|
|
static void *
|
|
stpc_init(const device_t *info)
|
|
{
|
|
stpc_log("STPC: init()\n");
|
|
|
|
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
|
|
memset(dev, 0, sizeof(stpc_t));
|
|
|
|
dev->local = info->local;
|
|
|
|
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
|
|
pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
|
|
if (dev->local & STPC_IDE_ATLAS)
|
|
pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
|
|
if (dev->local & STPC_USB) {
|
|
dev->usb = device_add(&usb_device);
|
|
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
|
|
}
|
|
|
|
stpc_setup(dev);
|
|
stpc_reset(dev);
|
|
|
|
smram[0].host_base = 0x000a0000;
|
|
smram[0].ram_base = 0x000a0000;
|
|
smram[0].size = 0x00020000;
|
|
|
|
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
|
|
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
|
|
|
|
stpc_smram_map(0, smram[0].host_base, smram[0].size, 0);
|
|
stpc_smram_map(1, smram[0].host_base, smram[0].size, 1);
|
|
|
|
device_add(&port_92_pci_device);
|
|
|
|
return dev;
|
|
}
|
|
|
|
|
|
const device_t stpc_client_device =
|
|
{
|
|
"STPC Client",
|
|
DEVICE_PCI,
|
|
STPC_NB_CLIENT | STPC_ISAB_CLIENT,
|
|
stpc_init,
|
|
stpc_close,
|
|
stpc_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|
|
|
|
const device_t stpc_consumer2_device =
|
|
{
|
|
"STPC Consumer-II",
|
|
DEVICE_PCI,
|
|
STPC_ISAB_CONSUMER2,
|
|
stpc_init,
|
|
stpc_close,
|
|
stpc_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|
|
|
|
const device_t stpc_elite_device =
|
|
{
|
|
"STPC Elite",
|
|
DEVICE_PCI,
|
|
0,
|
|
stpc_init,
|
|
stpc_close,
|
|
stpc_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|
|
|
|
const device_t stpc_atlas_device =
|
|
{
|
|
"STPC Atlas",
|
|
DEVICE_PCI,
|
|
STPC_IDE_ATLAS | STPC_USB,
|
|
stpc_init,
|
|
stpc_close,
|
|
stpc_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|