0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
180 lines
4.7 KiB
C
180 lines
4.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the UMC 491/493 chipset.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2020 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_UMC491_LOG
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int ali1429_do_log = ENABLE_UMC491_LOG;
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static void
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umc491_log(const char *fmt, ...)
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{
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va_list ap;
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if (umc491_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define umc491_log(fmt, ...)
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#endif
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typedef struct
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{
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uint8_t index,
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regs[256];
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} umc491_t;
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static void umc491_shadow_recalc(umc491_t *dev)
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{
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shadowbios = (dev->regs[0xcc] & 0x40);
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shadowbios_write = (dev->regs[0xcc] & 0x80);
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mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0xcd] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0xcd] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0xcd] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0xcd] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xd0000, 0x4000, ((dev->regs[0xce] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xd4000, 0x4000, ((dev->regs[0xce] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xd8000, 0x4000, ((dev->regs[0xce] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xdc000, 0x4000, ((dev->regs[0xce] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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/*
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Our machine has the E segment into parts although most AMI machines treat it as one.
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Probably a flaw by the BIOS as only one register gets enabled for it anyways.
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*/
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0xcc] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcc] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0xcc] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcc] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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flushmmucache();
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}
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static void
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umc491_write(uint16_t addr, uint8_t val, void *priv)
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{
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umc491_t *dev = (umc491_t *) priv;
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switch (addr) {
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case 0x8022:
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dev->index = val;
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break;
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case 0x8024:
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umc491_log("UMC 491: dev->regs[%02x] = %02x\n", dev->index, val);
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dev->regs[dev->index] = val;
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switch(dev->index)
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{
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case 0xcc:
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case 0xcd:
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case 0xce:
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umc491_shadow_recalc(dev);
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break;
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case 0xd0:
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cpu_update_waitstates();
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break;
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case 0xd1:
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cpu_cache_ext_enabled = (val & 0x01);
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break;
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}
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break;
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}
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}
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static uint8_t
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umc491_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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umc491_t *dev = (umc491_t *) priv;
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switch (addr) {
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case 0x8024:
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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static void
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umc491_close(void *priv)
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{
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umc491_t *dev = (umc491_t *) priv;
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free(dev);
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}
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static void *
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umc491_init(const device_t *info)
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{
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umc491_t *dev = (umc491_t *) malloc(sizeof(umc491_t));
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memset(dev, 0, sizeof(umc491_t));
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device_add(&port_92_device);
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/*
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UMC 491/493 Ports
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8022h Index Port
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8024h Data Port
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*/
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io_sethandler(0x8022, 0x0001, umc491_read, NULL, NULL, umc491_write, NULL, NULL, dev);
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io_sethandler(0x8024, 0x0001, umc491_read, NULL, NULL, umc491_write, NULL, NULL, dev);
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dev->regs[0xcc] = 0x00;
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dev->regs[0xcd] = 0x00;
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dev->regs[0xce] = 0x00;
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umc491_shadow_recalc(dev);
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return dev;
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}
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const device_t umc491_device = {
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"UMC 491/493",
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0,
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0,
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umc491_init, umc491_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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