552a87ea3d
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port; Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX); Finished the 586MC1; Added 8087 emulation; Moved Cyrix 6x86'es to the Dev branch; Sanitized/cleaned up memregs.c/h and intel.c/h; Split the chipsets from machines and sanitized Port 92 emulation; Added support for the 15bpp mode to the Compaq ATI 28800; Moved the MR 386DX and 486 machines to the Dev branch; Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00; Ported the new timer code from PCem; Cleaned up the CPU table of unused stuff and better optimized its structure; Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch; Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem; Added the AHA-1540A and the BusTek BT-542B; Moved the Sumo SCSI-AT to the Dev branch; Minor IDE, FDC, and floppy drive code clean-ups; Made NCR 5380/53C400-based cards' BIOS address configurable; Got rid of the legacy romset variable; Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit; Added the Amstead PPC512 per PCem patch by John Elliott; Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages); Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing; Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem; Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit; Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement; Amstrad MegaPC does now works correctly with non-internal graphics card; The SLiRP code no longer casts a packed struct type to a non-packed struct type; The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present; The S3 Virge on BeOS is no longer broken (was broken by build #1591); OS/2 2.0 build 6.167 now sees key presses again; Xi8088 now work on CGA again; 86F images converted from either the old or new variants of the HxC MFM format now work correctly; Hardware interrupts with a vector of 0xFF are now handled correctly; OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct; Fixed VNC keyboard input bugs; Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver; Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly; Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4; Compaq Portable now works with all graphics cards; Fixed various MDSI Genius bugs; Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly; Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355; OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400. Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391. Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389. Fixed a minor IDE timing bug, fixes #388. Fixed Toshiba T1000 RAM issues, fixes #379. Fixed EGA/(S)VGA overscan border handling, fixes #378; Got rid of the now long useless IDE channel 2 auto-removal, fixes #370; Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366; Ported the Unicode CD image file name fix from VARCem, fixes #365; Fixed high density floppy disks on the Xi8088, fixes #359; Fixed some bugs in the Hercules emulation, fixes #346, fixes #358; Fixed the SCSI hard disk mode sense pages, fixes #356; Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349; Fixed bugs in the serial mouse emulation, fixes #344; Compiled 86Box binaries now include all the required .DLL's, fixes #341; Made some combo boxes in the Settings dialog slightly wider, fixes #276.
620 lines
37 KiB
C
620 lines
37 KiB
C
#define OP_SHIFT_b(c, ea32) \
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{ \
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uint8_t temp_orig = temp; \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL b, c*/ \
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temp = (temp << (c & 7)) | (temp >> (8-(c & 7))); \
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seteab(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 1) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 7)) & 1) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x08: /*ROR b,CL*/ \
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temp = (temp >> (c & 7)) | (temp << (8-(c & 7))); \
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seteab(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 0x80) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL b,CL*/ \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x80; \
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temp = (temp << 1) | tempc; \
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR b,CL*/ \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x80 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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seteab(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x28: /*SHR b,CL*/ \
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seteab(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x38: /*SAR b,CL*/ \
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temp = (int8_t)temp >> c; \
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seteab(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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} \
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}
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#define OP_SHIFT_w(c, ea32) \
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{ \
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uint16_t temp_orig = temp; \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL w, c*/ \
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temp = (temp << (c & 15)) | (temp >> (16-(c & 15))); \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 1) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 15)) & 1) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x08: /*ROR w,CL*/ \
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temp = (temp >> (c & 15)) | (temp << (16-(c & 15))); \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 0x8000) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL w, c*/ \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x8000; \
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temp = (temp << 1) | tempc; \
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR w, c*/ \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x8000 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL w, c*/ \
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seteaw(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x28: /*SHR w, c*/ \
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seteaw(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x38: /*SAR w, c*/ \
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temp = (int16_t)temp >> c; \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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} \
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}
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#define OP_SHIFT_l(c, ea32) \
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{ \
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uint32_t temp_orig = temp; \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL l, c*/ \
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temp = (temp << c) | (temp >> (32-c)); \
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seteal(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 1) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 31)) & 1) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x08: /*ROR l,CL*/ \
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temp = (temp >> c) | (temp << (32-c)); \
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seteal(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp & 0x80000000) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL l, c*/ \
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temp2 = CF_SET(); \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x80000000; \
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temp = (temp << 1) | tempc; \
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x18: /*RCR l, c*/ \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x80000000 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL l, c*/ \
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seteal(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x28: /*SHR l, c*/ \
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seteal(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x38: /*SAR l, c*/ \
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temp = (int32_t)temp >> c; \
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seteal(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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} \
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}
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static int opC0_a16(uint32_t fetchdat)
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{
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int c;
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int tempc;
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uint8_t temp, temp2 = 0;
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fetch_ea_16(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c, 0);
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return 0;
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}
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static int opC0_a32(uint32_t fetchdat)
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{
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int c;
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int tempc;
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uint8_t temp, temp2 = 0;
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fetch_ea_32(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c, 1);
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return 0;
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}
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static int opC1_w_a16(uint32_t fetchdat)
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{
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int c;
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int tempc;
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uint16_t temp, temp2 = 0;
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fetch_ea_16(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c, 0);
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return 0;
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}
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static int opC1_w_a32(uint32_t fetchdat)
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{
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int c;
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int tempc;
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uint16_t temp, temp2 = 0;
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fetch_ea_32(fetchdat);
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if (cpu_mod != 3)
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c, 1);
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return 0;
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}
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static int opC1_l_a16(uint32_t fetchdat)
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{
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int c;
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int tempc;
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uint32_t temp, temp2 = 0;
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fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
|
PREFETCH_PREFIX();
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 0);
|
|
return 0;
|
|
}
|
|
static int opC1_l_a32(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint32_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
|
PREFETCH_PREFIX();
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opD0_a16(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint8_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_b(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD0_a32(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint8_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_b(c, 1);
|
|
return 0;
|
|
}
|
|
static int opD1_w_a16(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint16_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_w(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD1_w_a32(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint16_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_w(c, 1);
|
|
return 0;
|
|
}
|
|
static int opD1_l_a16(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint32_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD1_l_a32(uint32_t fetchdat)
|
|
{
|
|
int c = 1;
|
|
int tempc;
|
|
uint32_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opD2_a16(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint8_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_b(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD2_a32(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint8_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteab(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_b(c, 1);
|
|
return 0;
|
|
}
|
|
static int opD3_w_a16(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint16_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_w(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD3_w_a32(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint16_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteaw(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_w(c, 1);
|
|
return 0;
|
|
}
|
|
static int opD3_l_a16(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint32_t temp, temp2 = 0;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 0);
|
|
return 0;
|
|
}
|
|
static int opD3_l_a32(uint32_t fetchdat)
|
|
{
|
|
int c;
|
|
int tempc;
|
|
uint32_t temp, temp2 = 0;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod != 3)
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
c = CL & 31;
|
|
temp = geteal(); if (cpu_state.abrt) return 1;
|
|
OP_SHIFT_l(c, 1);
|
|
return 0;
|
|
}
|
|
|
|
|
|
#define SHLD_w() \
|
|
if (count) \
|
|
{ \
|
|
int tempc; \
|
|
uint32_t templ; \
|
|
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
|
|
tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
|
|
templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
|
|
if (count <= 16) tempw = templ >> (16 - count); \
|
|
else tempw = (templ << count) >> 16; \
|
|
seteaw(tempw); if (cpu_state.abrt) return 1; \
|
|
setznp16(tempw); \
|
|
flags_rebuild(); \
|
|
if (tempc) cpu_state.flags |= C_FLAG; \
|
|
}
|
|
|
|
#define SHLD_l() \
|
|
if (count) \
|
|
{ \
|
|
int tempc; \
|
|
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
|
|
tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
|
|
templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
|
|
seteal(templ); if (cpu_state.abrt) return 1; \
|
|
setznp32(templ); \
|
|
flags_rebuild(); \
|
|
if (tempc) cpu_state.flags |= C_FLAG; \
|
|
}
|
|
|
|
|
|
#define SHRD_w() \
|
|
if (count) \
|
|
{ \
|
|
int tempc; \
|
|
uint32_t templ; \
|
|
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
|
|
tempc = (tempw >> (count - 1)) & 1; \
|
|
templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
|
|
tempw = templ >> count; \
|
|
seteaw(tempw); if (cpu_state.abrt) return 1; \
|
|
setznp16(tempw); \
|
|
flags_rebuild(); \
|
|
if (tempc) cpu_state.flags |= C_FLAG; \
|
|
}
|
|
|
|
#define SHRD_l() \
|
|
if (count) \
|
|
{ \
|
|
int tempc; \
|
|
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
|
|
tempc = (templ >> (count - 1)) & 1; \
|
|
templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
|
|
seteal(templ); if (cpu_state.abrt) return 1; \
|
|
setznp32(templ); \
|
|
flags_rebuild(); \
|
|
if (tempc) cpu_state.flags |= C_FLAG; \
|
|
}
|
|
|
|
#define opSHxD(operation) \
|
|
static int op ## operation ## _i_a16(uint32_t fetchdat) \
|
|
{ \
|
|
int count; \
|
|
\
|
|
fetch_ea_16(fetchdat); \
|
|
if (cpu_mod != 3) \
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
|
count = getbyte() & 31; \
|
|
operation() \
|
|
\
|
|
CLOCK_CYCLES(3); \
|
|
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
|
|
return 0; \
|
|
} \
|
|
static int op ## operation ## _CL_a16(uint32_t fetchdat) \
|
|
{ \
|
|
int count; \
|
|
\
|
|
fetch_ea_16(fetchdat); \
|
|
if (cpu_mod != 3) \
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
|
count = CL & 31; \
|
|
operation() \
|
|
\
|
|
CLOCK_CYCLES(3); \
|
|
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
|
|
return 0; \
|
|
} \
|
|
static int op ## operation ## _i_a32(uint32_t fetchdat) \
|
|
{ \
|
|
int count; \
|
|
\
|
|
fetch_ea_32(fetchdat); \
|
|
if (cpu_mod != 3) \
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
|
count = getbyte() & 31; \
|
|
operation() \
|
|
\
|
|
CLOCK_CYCLES(3); \
|
|
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
|
|
return 0; \
|
|
} \
|
|
static int op ## operation ## _CL_a32(uint32_t fetchdat) \
|
|
{ \
|
|
int count; \
|
|
\
|
|
fetch_ea_32(fetchdat); \
|
|
if (cpu_mod != 3) \
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
|
count = CL & 31; \
|
|
operation() \
|
|
\
|
|
CLOCK_CYCLES(3); \
|
|
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
|
|
return 0; \
|
|
}
|
|
|
|
opSHxD(SHLD_w)
|
|
opSHxD(SHLD_l)
|
|
opSHxD(SHRD_w)
|
|
opSHxD(SHRD_l)
|